Wireless clock regeneration and synchronization
A method and apparatus are described for regenerating a local clock within a wireless module and synchronizing the local clock with a wireless host clock. For one embodiment, the wireless module generates a local clock, counts the cycles of the clock during a common timing reference period maintained wirelessly between the wireless module and the host, receives a count of the host clock during the same common timing reference period, and adjusts the local clock signal based upon a comparison of the two counts. For one embodiment, the wireless module further receives timing references from the host and, in addition, receives packets of audio samples from the host accompanied by a timestamp, the timestamp based upon the host timing reference, and outputs the audio sample at the time designated by the timestamp.
1. A method comprising:
receiving at a wireless module a signal representing a host clock having a host clock frequency;
generating a local clock signal having a local clock frequency within the wireless module;
setting the local clock frequency based on the host clock frequency;
establishing a timing reference period common to the wireless module and a host to form a common timing reference, wherein the common timing reference is maintained wirelessly over a wireless link by receiving at least two signals representing beacons as control signals, and establishing the timing reference period as a beacon period between the two signals representing the beacons;
receiving, from the host over the wireless link, a host clock count during a period of the common timing reference; and
adjusting the local clock signal based upon the host clock count to form an adjusted local clock signal.
2. The method of claim 1 , wherein receiving the signal representing the host clock frequency comprises:
receiving the signal representing the host clock frequency into a wireless speaker including the wireless module.
3. The method of claim 2 , further comprising:
receiving the signal representing the host clock frequency into a wireless speaker including the wireless module.
4. The method of claim 1 , wherein receiving the signal representing the host clock frequency comprises:
receiving the signal representing a derivative of the host clock frequency at the wireless module.
5. The method of claim 1 , further comprising:
deriving the host clock frequency at the wireless module based on a timestamp.
6. The method of claim 1 , wherein adjusting the local clock signal comprises:
comparing the local clock count and the host clock;
determining the local clock count and the host clock count are not equal; and
adjusting the local clock signal so that the local clock count matches the host clock count.
7. The method of claim 1 , wherein adjusting the local clock signal comprises:
comparing the local clock count and the host clock;
determining the local clock count and the host clock count are equal; and
using both the local clock count and the host clock count in another period of the common timing reference.
8. The method of claim 1 , further comprising:
generating an audio signal based the adjusted local clock signal; and
applying the audio signal to a wireless speaker including the wireless module to generate audio.
9. A wireless speaker comprising:
a wireless module comprising:
a radio configured to receive a signal representing a host clock having a host clock frequency;
control logic configured to:
establish a timing reference period common to the wireless module and a host to form a common timing reference based on beacon control signals, the common timing reference being maintained wirelessly over a wireless link;
determine a host clock count during a period of the common timing reference, wherein the common timing reference is maintained wirelessly via the radio over the wireless link;
set a local clock frequency based on a host clock frequency associated with the host clock count; and
adjusting a local clock signal based upon the host clock count to form an adjusted local clock signal; and
a phased-lock loop circuit configured to generate the adjusted local clock signal.