IP Library Granted Patent US 8,935,507
Granted Patent B2
US 8,935,507 · App. 13/959,711 · Granted Jan 13, 2015

System and method for storing multiple copies of data in a high speed memory system

Inventors: Sundar Iyer (Palo Alto, CA); Shang-Tse Chuang (Los Altos, CA)
Assignee: Memoir Systems, Inc.
G06F12/1009G11C7/1075G06F12/109
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Quick Facts
Patent No.
US 8,935,507
App. No.
13/959,711
Granted
Jan 13, 2015
Kind
B2
Abstract

A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by storing a second encoded copy of data in a multi-port XOR memory bank.

Claims (40)

1. A method of handling memory access requests in a digital memory system, said digital memory system comprising a multi-port XOR bank and a plurality of single-port memory banks wherein each of said plurality of memory single-port banks may operate concurrently and independent of each other, said method comprising:

receiving a memory write request having a first data item, said memory write request identifying a first memory address;

handling said first memory write request with said first memory address by

writing said first data item to said first memory address in a first memory bank in said plurality of single-port memory banks,

reading a first XOR data item from a first XOR bank location corresponding to said first memory address from said multi-port XOR bank,

XORing said first data item with said first XOR data item read from said first XOR bank location to create an XOR result and writing the XOR result back to said first XOR bank location;

receiving a first memory read request, said first memory read request identifying a second memory address; and

handling said first memory read request by reading from said second memory address if said second memory address is not located in said first memory bank.

2. The method of handling memory access requests as set forth in claim 1 wherein said digital memory system further comprises an XOR bank contents table.

3. The method of handling memory access requests as set forth in claim 2 wherein said XOR bank contents table and said plurality of memory single-port memory banks have an equal number of rows.

4. The method of handling memory access requests as set forth in claim 2 wherein each entry in said XOR bank contents table stores an indicator of whether a corresponding memory location contains valid data.

5. The method of handling memory access requests as set forth in claim 1 wherein said first physical memory address space comprises N memory banks and said plurality of single-port memory banks comprises N single-port memory banks.

6. The method of handling memory access requests as set forth in claim 1 wherein said second memory address is located in said first memory bank, said method handling said first memory read request by:

reading a second XOR data item from a second XOR bank location corresponding to said second memory address from said multi-port XOR bank;

reading an XOR bank contents table to determine valid data stored in said second XOR data item;

reading other row data from memory banks other than said first memory bank that contain said valid data; and

XORing said other row data from memory banks other than said first memory bank with said second XOR data item to decode a data item associated with said second memory address.

7. The method of handling memory access requests as set forth in claim 6 , said method further comprising:

clearing a flag in said XOR bank contents table corresponding to said second memory address;

XORing together said other row data from memory banks other than said first memory bank to create an XOR result and writing said XOR result into second XOR bank location corresponding to said second memory address from said multi-port XOR bank.

8. A digital memory system for handling memory access requests, said digital memory system comprising:

a plurality of single-port memory banks, each of said plurality of single-port memory banks able to operate concurrently and independent of each other;

a multi-port XOR bank, said multi-port XOR bank storing encoded copies of valid data stored in said single-port memory banks; and

a memory controller for operating said digital memory system, said memory controller comprising

an XOR bank contents table, said XOR bank contents table specifying which memory locations in said plurality of single-port memory banks have valid data stored in said multi-port XOR bank,

memory controller logic, said memory controller logic storing data in both said single-port memory banks and in said multi-port XOR bank.

9. The digital memory system for handling memory access requests as set forth in claim 8 wherein said XOR bank contents table comprises a set of columns equal to a number of single-port memory banks.

10. The digital memory system for handling memory access requests as set forth in claim 9 wherein said changeable XOR bank contents table and said plurality of single-port memory banks have an equal number of rows.

11. The digital memory system for handling memory access requests as set forth in claim 8 wherein encoded copies of valid data stored in said multi-port XOR bank comprises an XORed combination of data from corresponding rows of said single-port memory banks.

12. The digital memory system for handling memory access requests as set forth in claim 8 wherein said memory controller handles a write request of a first data item to a first memory address by writing said first data item to said first memory address in a first memory bank in said plurality of memory single-port banks, reading a first XOR data item from a first XOR bank location corresponding to said first memory address from said multi-port XOR bank, and XORing said first data item with said first XOR data item read from said first XOR bank location to create an XOR result and writing the XOR result back to said first XOR bank location.

13. The digital memory system for handling memory access requests as set forth in claim 8 said memory controller handles a read request to a second memory address by reading a second XOR data item from a second XOR bank location corresponding to said second memory address from said multi-port XOR bank, reading an XOR bank contents table to determine valid data stored in said second XOR data item, reading other row data from memory banks that store said valid data, XORing said other row data from memory banks with said second XOR data item to decode a data item associated with said second memory address.

14. A method of storing two copies of data in a digital memory system, said method comprising:

receiving a write request to write a first data item to a first memory address in said digital memory system;

writing said first data item to said first memory address in a first memory bank of a plurality of single-port memory banks;

reading a first XOR data item from a first XOR bank location corresponding to said first memory address from a multi-port XOR bank;

XORing said first data item with said first XOR data item read from said first XOR bank location to create an XOR result; and

writing the XOR result back to said first XOR bank location such that said first XOR bank location contains an encoded version of said first data item.

15. The method of storing two copies of data in a digital memory system as set forth in claim 14 further comprising:

setting a flag in an XOR bank contents table corresponding to said first memory address.

16. The digital memory system for handling memory access requests as set forth in claim 15 wherein said XOR bank contents table comprises a same number of entries as memory addresses in said plurality of single-port memory banks.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 035474 FRAME: 0122. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 24, 2015
From: MEMOIR SYSTEMS LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 035497/0188 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2015
From: CISCO TECHNOLOGY, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 035474/0122 →
CHANGE OF NAME Recorded Apr 22, 2015
From: MEMOIR SYSTEMS, INC.
To: MEMOIR SYSTEMS LLC
Reel/Frame 035479/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2014
From: IYER, SUNDAR; CHAUANG, SHANG-TSE
To: MEMOIR SYSTEMS, INC.
Reel/Frame 033704/0765 →
Continuity (4)
Continuation 13570125 · Aug 8, 2012
Continuation 12653660 · Dec 15, 2009
Continuation In Part 12584645 · Sep 8, 2009
Related Publication 20140310482A1 · Oct 16, 2014