Semiconductor device and structure

1. An Integrated Circuit device comprising:

a first layer of first transistors;

a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;

a second metal layer overlaying said first metal layer; and

a second layer of second transistors overlaying said second metal layer,

wherein said second metal layer is connected to provide power to at least one of said second transistors.

2. An Integrated Circuit device according to claim 1 , further comprising:

logic cells comprising said second transistors,

wherein at least one of said logic cells comprises a connection made by said second metal layer.

3. An Integrated Circuit device according to claim 1 , wherein at least one of said second transistors comprises a back-bias.

4. An Integrated Circuit device according to claim 1 , further comprising:

a connection path between said second transistors and said second metal layer, wherein said connection path comprises at least one through-layer via, and wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

5. An Integrated Circuit device according to claim 1 , wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor; or

(ii) a Finfet transistor.

6. An Integrated Circuit device according to claim 1 , further comprising:

at least one via through said second layer,

wherein said first layer comprises a first alignment mark, and

wherein said at least one via is aligned to said first alignment mark.

7. An Integrated Circuit device according to claim 1 , further comprising:

at least one via through said second layer,

wherein said at least one via is adapted to conduct heat.

8. An Integrated Circuit device comprising:

a first layer of first transistors;

a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;

a second metal layer overlaying said first metal layer;

a second layer of second transistors overlaying said second metal layer; and

a third metal layer overlying said second transistors,

wherein at least one of said second transistors is provided with a back-bias.

9. An Integrated Circuit device according to claim 8 , wherein said second metal layer is connected to provide power to at least one of said second transistors.

10. An Integrated Circuit device according to claim 8 , further comprising:

at least one via through said second layer,

wherein said at least one via is adapted to conduct heat.

11. An Integrated Circuit device according to claim 8 , further comprising:

at least one via through said second layer,

wherein said at least one via is forming a direct contact with at least one of said second transistors.

12. An Integrated Circuit device according to claim 8 , wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor;

(ii) a Finfet transistor; or

(iii) a double gate horizontally oriented transistor.

13. An Integrated Circuit device according to claim 8 , further comprising:

at least one via through said second layer,

wherein said first layer comprises a first alignment mark, and

wherein said at least one via is aligned to said first alignment mark.

14. An Integrated Circuit device comprising:

a first layer of first transistors;

a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;

a second metal layer overlaying said first metal layer;

a second layer of second transistors overlaying said second metal layer; and

a third metal layer overlying said second transistors,

wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor;

(ii) a Finfet transistor; or

(iii) a double gate horizontally oriented transistor.

15. An Integrated Circuit device according to claim 14 , further comprising:

a back-bias for at least one of said second transistors.

16. An Integrated Circuit device according to claim 14 , wherein said second metal layer is connected to provide power to at least one of said second transistors.

17. An Integrated Circuit device according to claim 14 , further comprising:

a connection path between said second transistors and said first transistors,

wherein said connection path comprises at least one through-layer via, and

wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

18. An Integrated Circuit device according to claim 14 , further comprising:

vias through said second layer,

wherein said vias are adapted to conduct heat.

19. An Integrated Circuit device according to claim 14 , further comprising:

at least one via through said second layer,

wherein said first layer comprises a first alignment mark, and

wherein said at least one via is aligned to said first alignment mark.

20. An Integrated Circuit device comprising:

a first layer of first transistors;

a first metal layer overlaying said first transistors and providing at least one connection to said first transistors;

a second metal layer overlaying said first metal layer;

a second layer of second transistors overlaying said second metal layer; and

a third metal layer overlying said second transistors,

wherein at least one of said second transistors is one of:

(i) a replacement-gate transistor; or

(ii) a Finfet transistor.

21. An Integrated Circuit device according to claim 20 wherein said second metal layer comprises copper or aluminum.

22. An Integrated Circuit device according to claim 20 , further comprising:

a back-bias for at least one of said second transistors.

23. An Integrated Circuit device according to claim 20 , wherein said second metal layer comprises a power grid to provide power to at least one of said second transistors.

24. An Integrated Circuit device according to claim 20 , further comprising:

at least one connection path between said second transistors and said second metal layer,

wherein said connection path comprises at least one through-layer via, and

wherein said through-layer via comprises material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said second layer.

25. An Integrated Circuit device according to claim 20 , further comprising:

at least one via through said second layer,

wherein said first layer comprises a first alignment mark, and

wherein said at least one via is aligned to said first alignment mark.