Memory module communication control
View Patent ↗Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle.
1. A system comprising:
a switch controller configured to:
receive a message associated with a memory module in communication with the switch controller via a bus including a clock line;
determine whether the bus is idle; and
communicate a signal via the clock line identifying the message associated with the memory module in response to determining that the bus is idle.
2. The system of claim 1 , wherein the switch controller is configured to receive a message comprises receiving an interrupt from the memory module.
3. The system of claim 1 , wherein the memory module is a dual in-line memory module (DIMM).
4. The system of claim 3 , wherein the switch controller is configured to receive an interrupt from the memory module.
5. The system of claim 1 , wherein the bus is an I 2 C bus.
6. The system of claim 1 , wherein the clock line is a serial clock line.
7. The system of claim 1 , wherein the switch controller is configured to drive the clock line low in response to receipt of the message.
8. A system comprising:
a switch controller configured to:
receive an interrupt for a memory module in communication with the switch controller via a bus including a clock line;
determine whether the bus is idle; and
in response to determining that the bus is not idle:
drive the clock line low; and
communicate a stop command to one or more other memory modules.
9. The system of claim 8 , wherein the memory module is a dual in-line memory module (DIMM).
10. The system of claim 8 , wherein the bus is an I 2 C bus.
11. The system of claim 8 , wherein the clock line is a serial clock line.
12. A system comprising:
a switch controller associated with a master device in a computer bus system, the switch controller configured to:
receive a signal identifying a message via a clock line; and
communicate the message identified in the signal to one or more other devices.
13. The system of claim 12 , wherein the message indicates receipt of an interrupt from a memory module.
14. The system of claim 12 , wherein the memory module is a dual in-line memory module (DIMM).
15. The system of claim 12 , wherein the computer bus system is an I 2 C bus system.
16. The system of claim 12 , wherein the clock line is a serial clock line.
17. The system of claim 12 , wherein the switch controller is configured to communicate the message to a platform controller hub.
18. The system of claim 17 , wherein the message is an interrupt.
19. The system of claim 12 , wherein the switch controller is configured to detect the signal on the clock line.
20. The system of claim 19 , wherein the switch controller is configured to detect that voltage on the clock line is driven below a predefined voltage level.