Memory module communication control
View Patent ↗Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle.
1. A method comprising:
receiving a message associated with a memory module in communication with a controller via a bus including a clock line;
determining whether the bus is idle; and
in response to determining that the bus is idle, communicating a signal via the clock line regarding the message associated with the memory module.
2. The method of claim 1 , wherein receiving a message comprises receiving an interrupt from the memory module.
3. The method of claim 1 , wherein the memory module is a dual in-line memory module (DIMM).
4. The method of claim 3 , wherein receiving a message comprises receiving an interrupt from the memory module.
5. The method of claim 1 , wherein the bus is an I 2 C bus.
6. The method of claim 1 , wherein the clock line is a serial clock line.
7. The method of claim 1 , wherein communicating a signal comprises driving the clock line low in response to receipt of the message.
8. A method comprising:
receiving an interrupt for a memory module in communication with a controller via a bus including a clock line;
determining whether the bus is idle; and
in response to determining that the bus is not idle:
driving the clock line low; and
communicating a stop command to one or more other memory modules.
9. The method of claim 8 , wherein the memory module is a dual in-line memory module (DIMM).
10. The method of claim 8 , wherein the bus is an I 2 C bus.
11. The method of claim 8 , wherein the clock line is a serial clock line.
12. A method comprising:
at a master device in a computer bus system:
receiving a signal via a clock line; and
communicating a message associated with the signal to one or more other devices.
13. The method of claim 12 , wherein the signal indicates receipt of an interrupt from a memory module.
14. The method of claim 12 , wherein the memory module is a dual in-line memory module (DIMM).
15. The method of claim 12 , wherein the computer bus system is an I 2 C bus system.
16. The method of claim 12 , wherein the clock line is a serial clock line.
17. The method of claim 12 , wherein communicating a message comprises communicating the message to a platform controller hub.
18. The method of claim 17 , wherein the message is an interrupt.
19. The method of claim 12 , further comprising detecting the signal on the clock line.
20. The method of claim 19 , wherein detecting the signal comprises detecting that voltage on the clock line is driven below a predefined voltage level.