Image sensor with hybrid heterostructure
View Patent ↗An image sensor architecture for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer includes the photodiode and amplifier circuitry for each pixel. A bottom includes the pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a process optimized for forming low-noise pixels, the pixel performance can be greatly improved. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a process which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter.
1. An image sensor comprising:
a PMOS circuit layer comprising an array of pixel elements;
each pixel element comprising :
a photodiode; and
a Capacitive Trans-Impedance Amplifier (CTIA) comprising P-FET transistors; and
a CMOS layer comprising supporting pixel circuitry, including a global shutter sample and hold circuit, the supporting pixel circuitry comprising N-FET transistors.
2. The image sensor of claim 1 , further comprising a blocking layer formed between the PMOS layer and the CMOS layer.
3. The image sensor of claim 2 , wherein the supporting pixel circuitry in the CMOS layer comprises a signal storage capacitor for each pixel, each signal storage capacitor is optically shielded by the blocking layer.
4. The image sensor of claim 2 , wherein the blocking layer comprises a plurality of capacitors, wherein a capacitor is electrically connected to a pixel element in the PMOS layer, and supporting pixel circuitry in the CMOS layer.
5. The image sensor of claim 2 , wherein the blocking layer is a metal layer formed as part of either the PMOS or CMOS layer.
6. The image sensor of claim 2 , wherein the blocking layer is a metal layer formed partially in both the PMOS layer and the CMOS layer.
7. The image sensor of claim 2 , wherein the CMOS layer further comprises digital circuitry formed along a periphery of the CMOS layer.
8. The image sensor of claim 2 , wherein the PMOS circuit layer further comprises:
Analog to Digital Converter (ADC) circuit portions comprising P-FETs.
9. The image sensor of claim 8 , wherein the PMOS circuit layer further comprises:
Column Buffer circuit portions comprising P-FETs.
10. The image sensor of claim 9 , wherein the CMOS circuit layer further comprises:
Analog to Digital Converter (ADC) circuit portions comprising N-FETs connected to corresponding ADC circuit portions in the PMOS layer.
11. The image sensor of claim 10 , wherein the CMOS circuit layer further comprises:
Column Buffer circuit portions comprising N-FETs connected to corresponding Column Buffer circuit portions in the PMOS layer.
12. The image sensor of claim 11 , wherein the CMOS layer further comprises digital circuitry formed along a periphery of the CMOS layer.
13. The image sensor of claim 12 , wherein the layers are bonded using Wafer on Wafer (WoW) bonding.
14. The image sensor of claim 2 further comprising a correlated double sampling (CDS) circuit comprising:
a correlated double sampling capacitor formed in the metal blocking layer; and
correlated double sampling circuitry formed in the CMOS layer.
15. The image sensor of claim 1 , wherein the sample and hold circuit comprises a trench capacitor formed in the CMOS layer.