Predicate counter

1. A processor, comprising:

a processing element;

a sequencer configured to provide a conditionally-executable instructions to the processing element, wherein a condition is provided by a predicate encoded in a predicate counter; and

a predicate counter register configured to receive more than two meaningful values and to provide its value as the predicate counter;

wherein the processor includes circuitry to provide IF, ELSE, and ENDIF primitives that are dependent on the predicate counter;

wherein the IF primitive comprises: receiving a condition; if the predicate counter is not zero, incrementing the predicate counter; if the predicate counter is zero and the condition is false, setting the predicate counter to one;

wherein the ELSE primitive comprises: if the predicate counter is zero, setting the predicate counter to one; and if the predicate counter is one, setting the predicate counter to zero;

wherein the ENDIF primitive comprises: if the predicate counter is not zero, decrementing the predicate counter.

2. The processor of claim 1 , further comprising:

a plurality of processing elements, wherein each processing element includes a predicate counter register, and wherein the processor is configured to operate in a single-instruction, multiple data (SIMD) mode.

3. The processor of claim 2 , wherein:

each processing element is divided into a plurality of/lanes;

the processor is configured to operate in SIMD-within-a-register mode; and

the processor further comprises a predicate counter group, wherein the predicate counter group contains at least n×l predicate counters, where n is the number of processing elements.

4. The processor of claim 1 , wherein the processor is configured to operate in a single-instruction, multiple-data within a register mode.

5. The processor of claim 1 , wherein the processor includes circuitry to implement LOOP and NEXT_STAGE primitives, wherein:

the LOOP primitive is configured to be executed before the first instruction of an unrolled stage loop; and

the NEXT_STAGE primitive is configured to be executed between stages of a pipelined stage loop.

6. The processor of claim 5 , wherein the LOOP primitive is configured to operate in a single-instruction, multiple-data-within-a-register (SWAR) mode, and wherein the LOOP primitive is configured to receive as a parameter a number of SWAR lanes.

7. A method performed by a computer, comprising:

receiving an instruction having associated therewith a predicate counter configured to receive more than two useful values;

if the predicate counter is a first value, executing the instruction; and

if the predicate counter is not the first value, ignoring the instruction;

executing IF, ELSE, and ENDIF primitives that are dependent on the predicate counter;

wherein: the IF primitive comprises: receiving a condition; if the predicate counter is not zero, incrementing the predicate counter; if the predicate counter is zero and the condition is false, setting the predicate counter to one;

the ELSE primitive comprises if the predicate counter is zero, setting the predicate counter to one; and if the predicate counter is one, setting the predicate counter to zero; and

the ENDIF primitive comprises: if the predicate counter is not zero, decrementing the predicate counter.

8. The method of claim 7 , wherein the first value is zero.

9. The method of claim 7 , wherein the first value is selected from the group consisting of zero, one, MAXINT, −MAXINT, infinity, negative infinity, and not-a-number.

10. The method of claim 7 , further comprising:

if the predicate counter is not the first value, taking additional action.

11. The method of claim 7 , further comprising:

executing a LOOP before the first instruction in a pipelined stage loop and a NEXT_STAGE primitive between stages of the unrolled loop, execution of the LOOP primitive and NEXT_STAGE primitive each being dependent on the predicate counter.

12. A non-transitory tangible computer-readable medium having stored thereon software instructions that, when executed, instruct a processor to:

read a predicate counter, the predicate counter having more than two useful values;

read a conditional instruction;

if the predicate counter is a first value, execute the instruction;

if the predicate counter is not the first value, ignore the instruction and manipulate the predicate counter based on the value of the predicate counter; and

executing IF, ELSE, and ENDIF primitives that are dependent on the predicate counter; wherein: the IF primitive comprises: receiving a condition; if the predicate counter is not zero, incrementing the predicate counter; if the predicate counter is zero and the condition is false, setting the predicate counter to one; the ELSE primitive comprises if the predicate counter is zero, setting the predicate counter to one; and if the predicate counter is one, setting the predicate counter to zero; and the ENDIF primitive comprises: if the predicate counter is not zero, decrementing the predicate counter.

13. The tangible computer-readable medium of claim 12 , wherein the manipulation is selected from the group consisting of incrementing, decrementing, and maintaining the value of the predicate counter.

14. The tangible computer-readable medium of claim 12 , further comprising a nested conditional branch configured to conditionally execute instructions based on a Boolean condition and on an integer nesting level indicated by the predicate counter.

15. The tangible computer-readable medium of claim 12 , further comprising an unrolled stage loop having a LOOP primitive at the head of the stage loop and a NEXT_STAGE primitive between each stage of the stage loop.

16. The tangible computer-readable medium of claim 12 , further comprising instructions using the predicate counter within a single-instruction, multiple-data-within-a-register operation.