Circuit and method for dynamic switching frequency adjustment in a power converter
View Patent ↗A method and a circuit dynamically adjust a frequency of a clock signal that drives the operations of a power converter. The method includes (a) detecting a change from a predetermined value in an output voltage of the power converter; and (b) upon detecting the change, changing the frequency of the clock signal so as to restore the output voltage. The change, such as a load step-up, may be detected by comparing a feedback signal generated from the output voltage and a predetermined threshold voltage. In one implementation, changing the switching frequency is achieved in increasing (e.g., doubling) the frequency of the clock signal, as needed. The frequency of the clock signal need only be changed for a predetermined time period.
1. A method for dynamically adjusting a frequency of a clock signal that determines a switching frequency of one or more switches in a power converter, comprising:
detecting a change from a predetermined steady state value in an output voltage of the power converter and indicating the change by an enable signal of a predetermined duration; and
upon receiving the enable signal, doubling the frequency of the clock signal by combining in time the clock signal with its complement for the predetermined duration, so as to increase the switching frequency of the switches, thereby restoring the output voltage to the predetermined steady state value.
2. The method of claim 1 , wherein detecting the change comprises comparing a feedback signal generated from the output voltage and a predetermined threshold voltage.
3. The method of claim 1 , wherein the change comprises a load step-up.
4. The method of claim 1 , wherein the change comprises a load step-down.
5. The method of claim 1 , wherein the power converter is a multi-phase power converter.
6. A circuit for dynamically adjusting a frequency of a clock signal that determines a switching frequency of one or more switches in a power converter, comprising:
detector circuit which indicates a change from a predetermined steady state value in an output voltage of the power converter by generating an enable signal of a predetermined duration; and
frequency adjusting circuit including a frequency doubler circuit which, upon the frequency adjustment circuit receiving the enable signal, is enabled to double the frequency of the clock signal by combining in time the clock signal with its complement for the predetermined duration, so as to increase the switching frequency of the switches, thereby restoring the output voltage to the predetermined steady state value.
7. The circuit of claim 6 , where the detector circuit compares a comparator that compares a feedback signal generated from the output voltage and a predetermined threshold voltage.
8. The circuit of claim 6 , wherein the change comprises a load step-up.
9. The circuit of claim 6 , further comprising a one-shot circuit which, upon detecting the change, provides the pulse of the predetermined duration during which to carry out doubling of the clock signal.
10. The circuit of claim 7 , wherein the power converter is a multi-phase power converter.