Method for manufacturing solid-state imaging device
View Patent ↗A solid-state imaging device comprising a semiconductor substrate; a logic circuit region having a first gate electrode; a pixel region having a plurality of pixel units, each which includes at least one second gate electrode; a first gate insulating film forming between the first gate electrode in the logic circuit region and the semiconductor substrate; a second gate insulating film forming between the second gate electrode in the pixel region and the semiconductor substrate; a first insulating layer covering the first gate electrode and the second gate electrode; and an offset spacer on a sidewall of the first gate electrode being formed by etch back of the first insulating layer on the first gate electrode.
1. A solid-state imaging device comprising:
a semiconductor substrate having a logic circuit region and a pixel transistor region;
a first gate electrode in the logic circuit region;
a pixel unit in the pixel transistor region, the pixel unit including at least one second gate electrode and a photoelectric conversion region in the substrate;
a first gate insulating film between the first gate electrode and the semiconductor substrate;
a second gate insulating film between the second gate electrode and the semiconductor substrate;
a first insulating layer in contact with each of the first gate electrode and the second gate electrode; and
sidewall insulating films comprised of a second insulating layer in the form of spacers adjacent the first and second gate electrodes with the first insulating layer between the first and second gate electrodes and the sidewall insulating films,
wherein,
in the logic circuit region, the first insulating layer is in the form of offset spacers adjacent the first gate electrode,
in the pixel region, a portion of the first insulating film is also between the sidewall insulating films and the semiconductor substrate, and
the sidewall insulating films are directly located on the portion of the first insulating layer between the sidewall insulating films and the semiconductor substrate.
2. The solid-state imaging device according to e claim 1 , wherein the first gate insulating film is thinner than the second gate insulating film.
3. The solid-state imaging device according to claim 1 , wherein the first gate insulating film is of the same material as the second gate insulating film.
4. The solid-state imaging device according to claim 1 , wherein the first gate electrode is smaller than the second gate electrode.
5. The solid-state imaging device according to claim 1 , wherein a surface of the substrate in the pixel region is not characterized by etch back damage.
6. The solid-state imaging device of claim 1 , wherein in the logic circuit section there is no portion of the first insulating layer between the sidewall insulating films and the semiconductor substrate.
7. The solid-state imaging device of claim 1 , wherein, in the pixel transistor region, the first insulating layer extends over an entire surface of the semiconductor substrate.
8. The solid-state imaging device of claim 6 , wherein, in the pixel transistor region, the first insulating layer extends over an entire surface of the semiconductor substrate.
9. The solid-state imaging device of claim 1 , wherein the first insulating layer covers the second gate electrode.
10. The solid-state imaging device of claim 9 , wherein the first insulating layer does not cover a top of the first gate electrode.
11. The solid-state imaging device of claim 7 , wherein the first insulating layer covers the second gate electrode.
12. The solid-state imaging device of claim 11 , wherein the first insulating layer does not cover a top of the first gate electrode.
13. A solid-state imaging device comprising:
a semiconductor substrate having a logic circuit region and a pixel transistor region;
a first gate electrode in the logic circuit region;
a pixel unit in the pixel transistor region, the pixel unit including at least one second gate electrode and a photoelectric conversion region in the substrate;
a first gate insulating film between the first gate electrode and the semiconductor substrate;
a second gate insulating film between the second gate electrode and the semiconductor substrate;
a first insulating layer in contact with each of the first gate electrode and the second gate electrode; and
sidewall insulting films comprised of a second insulating layer in the form of spacers adjacent the first and second gate electrodes with the first insulating layer between the first and second gate electrodes and the sidewall insulating films,
wherein,
in the logic circuit region, the first insulating layer is in the form of offset spacers adjacent the first gate electrode,
in the pixel region, a portion of the first insulating film is also between the sidewall insulating films and the semiconductor substrate,
in the pixel region, the sidewall insulating films are directly located on the portion of the first insulating layer sidewall insulating films and the semiconductor substrate,
in the logic circuit section, there is no portion of the first insulating layer between the sidewall insulating films and the semiconductor substrate,
in the pixel region, the first insulating layer extends over an entire surface of the semiconductor substrate, and
the first insulating layer covers the second gate electrode.
14. The solid-state imaging device of claim 13 , wherein the first insulating layer does not cover the a top of the first gate electrode.