Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

1. An apparatus comprising:

a hybrid memory module comprising

a non-volatile memory;

a volatile memory comprising a plurality of I/O buffers, wherein the volatile memory is configured to communicate using a first subset of the plurality of I/O buffers while in a first mode of operation and configured to communicate using a second subset of the plurality of I/O buffers while in a second mode of operation, wherein the volatile memory enters the second mode in response to control signals; and

a control circuit configured to transfer information from the volatile memory to the control circuit and from the control circuit to the non-volatile memory, wherein the control circuit communicates with the volatile memory using the second subset of I/O buffers, wherein the control circuit provides the control signals to the volatile memory to cause the volatile memory to enter the second mode.

2. The apparatus of claim 1 , wherein the non-volatile memory is configured to communicate with the control circuit via a non-volatile memory bus.

3. The apparatus of claim 2 , wherein the control circuit is configured to transfer data from the volatile memory to the non-volatile memory.

4. The apparatus of claim 1 , wherein the volatile memory includes a mode register configured to be programmed with information for setting the first mode of operation and further configured to be programmed with information for setting the second mode of operation.

5. The apparatus of claim 1 , wherein a storage capacity of the non-volatile memory is greater than a storage capacity of the volatile memory.

6. The apparatus of claim 1 , wherein the volatile memory comprises a plurality of memories.

7. The apparatus of claim 1 , further comprising a host configured to communicate with the hybrid memory module over the first subset of the plurality of I/O buffers.

8. A volatile memory comprising:

a first subset of I/O channels configured to be coupled to a first bus coupled to a host;

a first subset of I/O buffers configured to provide data to and receive data from the first subset of I/O channels;

a second subset of I/O channels configured to be coupled to a control circuit for transferring information from the memory to the control circuit;

a second subset of I/O buffers configured to provide data to and receive data from the second subset of I/O channels,

a mode register configured to be programmed with information to set a first mode of operation for the first subset of I/O channels and to be programmed with information to set a second mode of operation for the second subset of I/O channels; and

control logic coupled to the mode register and configured to enable communication via the first subset of I/O channels responsive to the first mode being set and to enable communication via the second subset of I/O channels responsive to the second mode being set via control signals from the control circuit, wherein the control logic is further configured to enable the first subset of I/O buffers for the first mode and to enable the second subset of I/O buffers for the second mode.

9. The memory of claim 8 , wherein the control logic is configured to enable communication via the first and second subsets of I/O buffers concurrently.

10. The memory of claim 8 , wherein the control logic is configured to enable communication via one of the first and second subsets of I/O buffers by programming the mode register with information to set the first mode or the second mode, respectively.

11. A hybrid memory module comprising:

a plurality of volatile memory each configured to communicate using, based on a mode of operation, one of a first subset of respective I/O buffers coupled to a host or a second subset of the respective I/O buffers, wherein a volatile memory of the plurality of volatile memory is configured to change a mode of operation in response to control signals; and

a control circuit configured to communicate with the plurality of volatile memory via the second subset of the respective I/O buffers and to transfer information between the plurality of volatile memory and the control circuit and to transfer the information between the control circuit and one or more non-volatile memories, wherein the control circuit provides the control signals to the volatile memory to cause the volatile memory to change the mode of operation.

12. The hybrid memory module of claim 11 , wherein first subset of the respective I/O buffers are configured to be coupled to a host bus.

13. The hybrid memory module of claim 11 , wherein a volatile memory of the plurality of volatile memory includes a mode register configured to be programmed with information to set the mode of operation.

14. The hybrid memory module of claim 11 , further comprising a non-volatile memory coupled to control circuit and configured to communicate with the control circuit via a non-volatile memory bus.

15. The hybrid memory module of claim 11 , wherein the control circuit comprises a field programmable gate array or an application specific integrated circuit.

16. The hybrid memory module of claim 11 , the plurality of volatile memory comprises a plurality of DRAM.

17. An apparatus comprising:

non-volatile memory;

a control circuit coupled to the non-volatile memory and configured to provide control signals to change a mode of operation; and

volatile memory comprising a plurality of I/O buffers, the volatile memory coupled to the control circuit and configured to enable a first subset of the plurality of I/O buffers for communication with a bus and enable a second subset of the plurality of I/O buffers for communication with the control circuit in response to receipt of the control signals to change the mode of operation, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory through the control circuit.

18. The apparatus of claim 17 , wherein the control circuit is configured to perform error calculations for information transferred between the volatile memory and the non-volatile memory.

19. The apparatus of claim 17 , wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory during a power failure event.

20. The apparatus of claim 17 , wherein the non-volatile memory, the control circuit, and the volatile memory are included in a memory module.

21. The apparatus of claim 17 , wherein the volatile memory is configured to enable the first subset of the plurality of I/O buffers for communication responsive to the volatile memory being set in a first mode of operation and configured to enable the second subset of the plurality of I/O buffers for communication responsive to the volatile memory being set in a second mode of operation.

22. The apparatus of claim 17 , wherein the plurality of I/O buffers includes I/O buffers (m+1) and the first subset of I/O buffers includes I/O buffers 0−k and the second subset of I/O buffers includes I/O buffers (k+1)−m.

23. A method, comprising:

transferring information from a host via a first subset of I/O buffers of a volatile memory of a hybrid memory module while the volatile memory is in a first mode of operation; and

transferring information to a control circuit of the hybrid memory module via a second subset of I/O buffers of the volatile memory while the volatile memory is in a second mode of operation, wherein the second mode of operation is enabled via control signals from the control circuit.

24. The method of claim 23 , further comprising:

enabling communication via the first subset of I/O buffers of the volatile memory responsive to the first mode of operation;

disabling communication via the second subset of I/O buffers of the volatile memory responsive to the first mode of operation;

disabling communication via the first subset of I/O buffers of the volatile memory responsive to the second mode of operation; and

enabling communication via the second subset of I/O buffers of the volatile memory responsive to the second mode of operation in response to the control signals received from the control circuit.

25. The method of claim 23 , further comprising detecting the second mode of operation based on information programmed in a mode register of the volatile memory.

26. The method of claim 23 , further comprising transferring information from the volatile memory to a non-volatile memory of the hybrid memory module via the control circuit while the volatile memory is in the second mode of operation.

27. The method of claim 23 , further comprising receiving information for programming to a mode register of the volatile memory for setting the first mode of operation or the second mode of operation.

28. The method of claim 23 , wherein the first mode of operation is a normal mode of operation, and wherein the second mode of operation is set for a power failure event.

29. A method, comprising:

configuring a volatile memory to communicate via a first subset of I/O buffers coupled to a host responsive to a first mode of operation; and

configuring the volatile memory to communicate via a second subset of I/O buffers responsive to a second mode of operation in response to control signals received from a control circuit,

wherein configuring the volatile memory to communicate via the second subset of I/O buffers comprises configuring the volatile memory to transfer information to the control circuit via the second subset of I/O buffers.

30. The method of claim 29 , wherein configuring the volatile memory to communicate via the first subset of I/O buffers comprises programming information to a mode register of the volatile memory to set the first mode of operation and wherein configuring the volatile memory to communicate via the second subset of I/O buffers comprises programming information to the mode register to set the second mode of operation.

31. The method of claim 29 , wherein configuring the volatile memory to communicate via the second subset of I/O buffers comprises configuring the volatile memory to communicate via the second subset of I/O buffers responsive to a power failure event.

32. The method of claim 29 , further comprising:

providing information to the volatile memory when the volatile memory is set in the first mode of operation.