Fan speed and memory regulator control based on memory margin
View Patent ↗Methods and systems for fan speed control based on memory margin are disclosed. According to an aspect, a method includes determining an operating margin of a memory interface. The method also includes determining whether the operating margin of the memory interface meets a predetermined condition. Further, the method includes controlling a speed of a computing system cooling fan based on the operating margin in response to determining the operating margin meets the predetermined condition.
1. A method comprising:
determining an operating margin of a memory interface;
determining whether the operating margin of the memory interface meets a predetermined condition; and
in response to determining the operating margin meets the predetermined condition, controlling a speed of a computing system cooling fan based on the operating margin.
2. The method of claim 1 , wherein determining an operating margin of the memory interface comprises:
writing a test pattern over the memory interface into the memory;
reading the test pattern from the memory to generate a read pattern; and
determining error based on a comparison of the read test pattern to the written test pattern, and
wherein controlling a speed of a computing system cooling fan comprises controlling the speed of the computing system cooling fan based on the determined error.
3. The method of claim 2 , further comprising varying the test pattern to determine the error.
4. The method of claim 3 , wherein varying the test pattern comprises varying one of receiver voltage and timing thresholds.
5. The method of claim 3 , wherein varying the test pattern comprises varying one of transmitter voltage and timing levels.
6. The method of claim 1 , wherein controlling a speed of a computing system cooling fan comprises using a baseboard management controller to control the speed of the computing system cooling fan.
7. The method of claim 1 , wherein determining an operating margin comprises determining the operating margin during system initialization.
8. The method of claim 1 , further comprising:
determining system initialization of a system associated with the memory interface; and
in response to determining the system initialization, implementing the steps of determining an operating margin of the memory interface and determining whether the operating margin of the memory interface meets a predetermined condition.
9. The method of claim 1 , further comprising receiving BIOS output, and
wherein determining whether the operating margin of the memory interface meets a predetermined condition comprises:
determining statistics associated with the operating margin based on the BIOS output; and
determining whether the operating margin meets the predetermined condition based on the statistics.
10. The method of claim 1 , wherein determining whether the operating margin of the memory interface meets a predetermined condition comprises determining whether the operating margin is greater than a predetermined level, and
wherein controlling a speed of a computing system cooling fan comprises reducing the speed of the computing system cooling fan in response to determining whether the operating margin is greater than the predetermined level.
11. A system comprising:
a computing device configured to:
determine an operating margin of a memory interface;
determine whether the operating margin of the memory interface meets a predetermined condition; and
control a speed of a computing system cooling fan based on the operating margin in response to determining the operating margin meets the predetermined condition.
12. The system of claim 11 , wherein the computing device is configured to:
write a test pattern over the memory interface into the memory;
read the test pattern from the memory to generate a read pattern;
determine error based on a comparison of the read test pattern to the written test pattern; and
control the speed of the computing system cooling fan based on the determined error.
13. The system of claim 12 , wherein the computing device is configured to vary the test pattern to determine the error.
14. The system of claim 13 , wherein the computing device is configured to vary one of receiver voltage and timing thresholds.
15. The system of claim 13 , wherein the computing device is configured to vary transmitter voltage and timing levels.
16. The system of claim 11 , wherein the computing device is configured to use a baseboard management controller to control the speed of the computing system cooling fan.
17. The system of claim 11 , wherein the computing device is configured to determine the operating margin during system initialization.
18. The system of claim 11 , wherein the computing device is configured to:
determine system initialization of a system associated with the memory interface; and
implement the functions of determining an operating margin of the memory interface and determining whether the operating margin of the memory interface meets a predetermined condition in response to determining the system initialization.
19. A method comprising:
determining an operating margin of a memory interface;
determining whether the operating margin of the memory interface meets a predetermined condition; and
in response to determining the operating margin meets the predetermined condition, controlling a memory regulator output based on the operating margin.
20. The method of claim 19 , wherein controlling a memory regulator output comprises reducing the memory regulator output based on an amount of the operating margin.