Passivation for group III-V semiconductor devices having a plated metal layer over an interlayer dielectric layer
A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.
1. A semiconductor device, comprising: a Group III-V semiconductor substrate; a first metal layer over the substrate; a planarizing interlayer dielectric layer over the first metal layer, the interlayer dielectric layer defining a via extending therethrough to the first metal layer; a second metal layer, greater in thickness than the first metal layer, over the interlayer dielectric layer the second metal layer comprising an interconnect extending through the via into contact with the first metal layer, the second metal layer patterned to define at least one conductor; and a passivation layer over the second metal layer and the interlayer dielectric layer, the passivation layer comprising stacked regions of dielectric material, ones of regions under tensile stress alternating with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.
2. The semiconductor device of claim 1 , in which:
the passivation layer is a second passivation layer;
the semiconductor device additionally comprises a first passivation layer between the interlayer dielectric layer and the second metal layer; and
the interconnect additionally extends through the first passivation layer.
3. The semiconductor device of claim 2 , in which the second metal layer is on the first passivation layer.
4. The semiconductor device of claim 2 , in which, at the interconnect, the second metal layer extends laterally over the first passivation layer, and contacts the first passivation layer to form a seal that encloses the via.
5. The semiconductor device of claim 2 , in which the second metal layer comprises an annular portion extending laterally over the first passivation layer around the via, the annular portion contacting the first passivation layer to form a seal that encloses the via.
6. The semiconductor device of claim 2 , in which the regions constituting the second passivation layer continuously cover corners between the first passivation layer and the second metal layer.
7. The semiconductor device of claim 2 , in which the second passivation layer comprises plasma-deposited silicon nitride, silicon dioxide, or silicon oxynitride.
8. The semiconductor device of claim 2 , in which the ones of the regions under tensile stress differ in thickness from the ones of the regions under compressive stress.
9. The semiconductor device of claim 1 , in which the second metal layer comprises plated gold.
10. The semiconductor device of claim 1 , in which the second metal layer comprises an annular portion extending across the interlayer dielectric layer around the via, the annular portion contacting the interlayer dielectric layer to form a seal that encloses the via.
11. The semiconductor device of claim 1 , in which the regions constituting the passivation layer continuously cover corners between the interlayer dielectric layer and the second metal layer.
12. The semiconductor device of claim 1 , in which the ones of the regions under tensile stress differ in thickness from the ones of the regions under compressive stress.
13. The semiconductor device of claim 1 , in which the interlayer dielectric layer comprises a polymer.
14. A semiconductor device, comprising: a Group III-V semiconductor substrate; a first metal layer over the substrate; a planarizing interlayer dielectric layer over the first metal layer; a first passivation layer over the interlayer dielectric layer, the first passivation layer and the interlayer dielectric layer defining a via extending therethrough to the first metal layer; a second metal layer, greater in thickness than the first metal layer, on the first passivation layer, the second metal layer comprising an interconnect extending through the via into contact with the first metal layer, the second metal layer patterned to define at least one conductor; and a second passivation layer over the second metal layer and the first passivation layer, the second passivation layer comprising stacked regions of dielectric material, ones of regions under tensile stress alternating with ones of the regions under compressive stress, such that the second passivation layer is subject to net compressive stress.
15. The semiconductor device of claim 14 , in which the second metal layer comprises an annular portion extending laterally across the first passivation layer around the via, the annular portion contacting the first passivation layer to form a seal that encloses the via.
16. The semiconductor device of claim 14 , in which the regions constituting the second passivation layer continuously cover corners between the first passivation layer and the second metal layer.
17. The semiconductor device of claim 14 , in which the second passivation layer comprises plasma-deposited silicon nitride, silicon dioxide, or silicon oxynitride.
18. The semiconductor device of claim 14 , in which the ones of the regions under tensile stress differ in thickness from the ones of the regions under compressive stress.
19. The semiconductor device of claim 14 , in which the second metal layer comprises plated gold.