Microcontroller programmable system on a chip with programmable interconnect
View Patent ↗Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
1. An integrated circuit comprising:
a plurality of programmable analog blocks;
a plurality of programmable digital blocks;
a programmable interconnect coupled to at least one of the programmable analog blocks and at least one of the programmable digital blocks;
a programmable Input/Output (I/O) interface coupled to the programmable interconnect and
a plurality of configuration register bits coupled to the programmable I/O interface.
2. The integrated circuit of claim 1 , further comprising a programmable system timing block coupled to the programmable interconnect.
3. The integrated circuit of claim 2 , wherein the programmable system timing block is configured to provide a clock signal to at least one programmable analog or programmable digital block.
4. The integrated circuit of claim 1 , further comprising a temperature sensor coupled to at least one programmable analog block.
5. The integrated circuit of claim 1 , wherein the plurality of programmable analog blocks comprise a first programmable analog block type and a second programmable analog block type.
6. The integrated circuit of claim 5 , wherein the first programmable analog block type comprises a switched capacitor circuit and the second programmable analog block type comprises a continuous time circuit.
7. The integrated circuit of claim 1 , wherein the programmable I/O interface comprises an input bus and an output bus.
8. The integrated circuit of claim 1 , wherein the operation of the plurality of programmable analog blocks is controlled by the plurality of programmable register bits.
9. The integrated circuit of claim 1 , wherein the operation of the plurality of programmable digital blocks is controlled by the plurality of programmable register bits.
10. The integrated circuit of claim 1 , wherein the connectivity of the programmable interconnect is controlled by the plurality of programmable register bits.
11. A method of configuring an integrated circuit comprising:
providing a plurality of programmable analog blocks of a first type;
providing a plurality of programmable digital blocks;
providing a programmable interconnect coupled to at least one of the programmable analog blocks and at least one of the programmable digital blocks;
providing a programmable Input/Output (I/O) interface coupled to the programmable interconnect;
providing a plurality of configuration register bits coupled to the programmable I/O interface and
configuring the plurality of programmable register bits to control the operation of the integrated circuit.
12. The method of claim 11 , further comprising providing a programmable system timing block and coupling the programmable system timing block to the programmable interconnect.
13. The method of claim 12 , further comprising configuring the programmable system timing block to provide a clock signal to at least one programmable analog or programmable digital block.
14. The method of claim 11 , further comprising providing a temperature sensor and coupling the temperature sensor to at least one programmable analog block.
15. The method of claim 11 , further comprising providing a plurality of programmable analog blocks of a second type.
16. The method of claim 11 , further comprising providing an I/O input bus and an I/O output bus within the I/O interface.
17. The integrated circuit of claim 11 , further comprising loading at least some of the programmable register bits with data retrieved from a non-volatile memory.
18. A system comprising:
a microprocessor coupled to a system bus;
a plurality of programmable analog blocks;
a plurality of programmable digital blocks;
a programmable interconnect coupled to at least one of the programmable analog blocks and at least one of the programmable digital blocks and to the system bus;
a programmable Input/Output (I/O) interface coupled to the programmable interconnect and
a plurality of configuration register bits coupled to the system bus.
19. The system of claim 18 , further comprising a non-volatile memory coupled to the microprocessor, wherein the microprocessor is configured to retrieve configuration data from the non-volatile memory and load the configuration data into the plurality of configuration register bits.
20. The system of claim 18 , further comprising a system timing block coupled to the programmable interconnect and configured to provide a clock signal to at least one programmable digital or programmable analog block.