IP Library Granted Patent US 9,258,202
Granted Patent B2
US 9,258,202 · App. 13/966,092 · Granted Feb 9, 2016

Correlation of performance monitoring records for logical end points within a protected group

Inventors: Simmon Yau (Lawrenceville, GA); Satish M. Gopalakrishna (Alpharetta, GA); Yossi Joseph Khalon (Alpharetta, GA); Matthew W. Connolly (Canton, GA)
Assignee: Ciena Corporation
H04L43/0847H04L1/00H04L41/065H04L41/0663G06F11/0709H04L41/0613
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Quick Facts
Patent No.
US 9,258,202
App. No.
13/966,092
Granted
Feb 9, 2016
Kind
B2
Abstract

A network system comprising logical work and protect Connection Termination Points. Performance Monitoring (PM) records are provided by generating for each work Connection Termination Point (CTP) a work bit vector and a protect bit vector. The work bit vector keeps track of severely errored seconds (SES) occurrences at the work CTP only when the work CTP is selected. The protect bit vector keeps track of severely errored seconds (SES) occurrences at the protect CTP only when the protect CTP is selected. Processing the work bit vector and the protect bit vector provides accurate PM records.

Claims (58)

1. A method comprising:

initializing a work bit vector associated with a work Connection Termination Point (CTP) in a group protected by a protect CTP;

initializing a protect bit vector;

recording occurrences of severely errored seconds (SES) in corresponding bit positions of the work bit vector only if the work CTP is selected for data traffic;

recording SES occurrences in corresponding bit positions of the protect bit vector only if the protect CTP is selected for data traffic; and

forming the union of the work bit vector and the protect bit vector to generate a correlated bit vector.

2. The method of claim 1 , wherein initializing the work bit vector includes setting the work bit vector to an all zero bit vector, and wherein initializing the protect bit vector includes setting the protect bit vector to the all zero bit vector.

3. The method of claim 1 , wherein forming the union of the work bit vector and the protect bit vector includes masking and forming a bit-wise logical OR of the work bit vector and the protect bit vector.

4. The method of claim 1 , further comprising:

initializing an SES correlated counter;

initializing an unavailable seconds (UAS) correlated counter;

processing bit values in the correlated bit vector according to a finite state machine (FSM), the FSM having states B(n) and C(n), wherein n is an integer index in the range 0 to N−1;

initializing the FSM to B(0) upon initialization of the SES correlated counter and the UAS correlated counter;

transitioning to B(n+1) if a processed bit value when in B(n) indicates an SES occurrence, where n in the range 0 through N−2;

incrementing the SES correlated counter for each transition from B(n) to B(n+1) for n in the range 0 through N−2; and

transitioning to B(0) if a processed bit value when in B(n) indicates no SES occurrence, where n in the range 0 through N−1.

5. The method of claim 4 , wherein initializing the SES correlated counter includes setting the SES correlated counter to 0, and wherein initializing the UAS correlated counter includes setting the UAS correlated counter to 0.

6. The method of claim 4 , further comprising:

transitioning to C(0) if a processed bit value when in B(N−1) indicates an SES occurrence;

decrementing the SES correlated counter by N and incrementing the UAS correlated counter by N for each transition from B(N−1) to C(0);

transitioning to C(0) if a processed bit value when in C(n) indicates an SES occurrence, where n in the range of 0 to N−1;

transitioning to C(n+1) if a processed bit value when in C(n) indicates no SES occurrence, where n in the range 0 through N−2;

incrementing the UAS correlated counter for each transition from C(m) to C(n), where m and n in the range 0 to N−1;

transitioning to B(0) if a processed bit value when in C(N−1) indicates no SES occurrence; and

decrementing the UAS correlated counter by N for each transition from C(N−1) to B(0).

7. An apparatus comprising at least one processor and a memory implemented in hardware, the apparatus to provide a work Connection Termination Point (CTP) in a group protected by a protect CTP, the memory comprising instructions that when executed by the at least one processor causes the apparatus to perform a method comprising:

initializing a work bit vector associated with the work Connection Termination Point (CTP) in the group protected by the protect CTP;

initializing a protect bit vector;

recording occurrences of severely errored seconds (SES) in corresponding bit positions of the work bit vector only if the work CTP is selected for data traffic;

recording SES occurrences in corresponding bit positions of the protect bit vector only if the protect CTP is selected for data traffic; and

forming the union of the work bit vector and the protect bit vector to generate a correlated bit vector.

8. The apparatus of claim 7 , wherein initializing the work bit vector includes setting the work bit vector to an all zero bit vector, and wherein initializing the protect bit vector includes setting the protect bit vector to the all zero bit vector.

9. The apparatus of claim 7 , wherein forming the union of the work bit vector and the protect bit vector includes masking and forming a bit-wise logical OR of the work bit vector and the protect bit vector.

10. The apparatus of claim 7 , the method further comprising:

initializing an SES correlated counter;

initializing an unavailable seconds (UAS) correlated counter;

processing bit values in the correlated bit vector according to a finite state machine (FSM), the FSM having states B(n) and C(n), wherein n is an integer index in the range 0 to N−1;

initializing the FSM to B(0) upon initialization of the SES correlated counter and the UAS correlated counter;

transitioning to B(n+1) if a processed bit value when in B(n) indicates an SES occurrence, where n in the range 0 through N−2;

incrementing the SES correlated counter for each transition from B(n) to B(n+1) for n in the range 0 through N−2; and

transitioning to B(0) if a processed bit value when in B(n) indicates no SES occurrence, where n in the range 0 through N−1.

11. The apparatus of claim 10 , wherein initializing the SES correlated counter includes setting the SES correlated counter to 0, and wherein initializing the UAS correlated counter includes setting the UAS correlated counter to 0.

12. The apparatus of claim 10 , the method further comprising:

transitioning to C(0) if a processed bit value when in B(N−1) indicates an SES occurrence;

decrementing the SES correlated counter by N and incrementing the UAS correlated counter by N for each transition from B(N−1) to C(0);

transitioning to C(0) if a processed bit value when in C(n) indicates an SES occurrence, where n in the range of 0 to N−1;

transitioning to C(n+1) if a processed bit value when in C(n) indicates no SES occurrence, where n in the range 0 through N−2;

incrementing the UAS correlated counter for each transition from C(m) to C(n), where m and n in the range 0 to N−1;

transitioning to B(0) if a processed bit value when in C(N−1) indicates no SES occurrence; and

decrementing the UAS correlated counter by N for each transition from C(N−1) to B(0).

13. A non-transitory, computer readable storage medium having instructions stored thereon that when executed by at least one processor cause the at least one processor to perform a method comprising:

initializing a work bit vector associated with a work Connection Termination Point (CTP) in a group protected by a protect CTP;

initializing a protect bit vector;

recording occurrences of severely errored seconds (SES) in corresponding bit positions of the work bit vector only if the work CTP is selected for data traffic;

recording SES occurrences in corresponding bit positions of the protect bit vector only if the protect CTP is selected for data traffic; and

forming the union of the work bit vector and the protect bit vector to generate a correlated bit vector.

14. The non-transitory, computer readable storage medium of claim 13 , wherein initializing the work bit vector includes setting the work bit vector to an all zero bit vector, and wherein initializing the protect bit vector includes setting the protect bit vector to the all zero bit vector.

15. The non-transitory, computer readable storage medium of claim 13 , wherein forming the union of the work bit vector and the protect bit vector includes masking and forming a bit-wise logical OR of the work bit vector and the protect bit vector.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2023
From: BANK OF AMERICA, N.A.
To: CIENA CORPORATION
Reel/Frame 065630/0232 →
PATENT SECURITY AGREEMENT Recorded Nov 8, 2019
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 050969/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 30, 2019
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: CIENA CORPORATION
Reel/Frame 050938/0389 →
PATENT SECURITY AGREEMENT Recorded Jul 16, 2014
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 033347/0260 →
SECURITY INTEREST Recorded Jul 15, 2014
From: CIENA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 033329/0417 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2013
From: YAU, SIMMON; GOPALAKRISHNA, SATISH M.; KHALON, YOSSI JOSEPH; CONNOLLY, MATTHEW W.
To: CIENA CORPORATION
Reel/Frame 031001/0992 →
Continuity (1)
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