Digital Phase Locked Loop with Hybrid Delta-Sigma Phase/Frequency Detector
A PLL includes independent frequency-locking and phase-locking operational modes. In addition, the PLL includes a hybrid (e.g., mixed-analog/digital signal) 2nd-order delta-sigma (DS) phase/frequency detector. The detector may be implemented based on a continuous-time 1st-order DS Analog to Digital (ADC) converter. The ADC may be enhanced to 2nd-order by using, e.g., closed loop frequency detection. The PLL includes a fine resolution encoder for encoding the DS ADC output. The fine resolution encoding facilitates true multi-bit phase/frequency error digitization with drastically reduced DS quantization noise.
1 . A phase locked loop (PLL) comprising:
a reference frequency input;
a detector in communication with the reference frequency input, the detector comprising a fine resolution encoder configured to output a multiple bit resolution phase/frequency error encoding;
a loop filter following the detector and configured to accept the multiple bit resolution error encoding; and
a reference frequency output following the loop filter.
2 . The PLL of claim 1 , where the detector comprises a phase and frequency detector including an analog to digital converter (ADC).
3 . The PLL of claim 2 , where the ADC is configured to selectively operate in:
a fine resolution mode providing a fine mode number of quantization levels; and
a coarse resolution mode providing fewer quantization levels than the fine mode number of quantization levels.
4 . The PLL of claim 3 , where the coarse resolution mode provides at least two quantization levels.
5 . The PLL of claim 3 , where the fine resolution mode provides at least eight quantization levels.
6 . The PLL of claim 2 , where the ADC comprises a delta-sigma ADC.
7 . The PLL of claim 6 , where the detector further comprises a charge pump configured to drive the delta-sigma ADC.
8 . The PLL of claim 1 , further comprising a digitally controller oscillator (DCO) driven by the loop filter, the DCO configured to generate a target output frequency signal on the target frequency output.
9 . The PLL of claim 8 , further comprising:
a feedback path from the DCO to the detector, the feedback path configured to provide the target frequency output to the detector.
10 . The PLL of claim 9 , where the feedback path comprises a multi-modulus divider (MMD) configured to receive the target frequency output.
11 . The PLL of claim 10 , further comprising a dither circuit configured to interface the fine resolution encoder to the MMD.
12 . The PLL of claim 11 , where the multi-modulus divider comprises a divider output that provides feedback to a phase and frequency detector (PFD) charge pump.
13 . The PLL of claim 12 , where the PFD charge pump drives a delta-sigma ADC in communication with the fine resolution encoder.
14 . A method comprising:
performing phase/frequency detection with respect to a reference frequency and a feedback signal;
generating, with a fine resolution encoder, a multiple bit error encoding of phase/frequency error responsive to the detection;
receiving the multiple bit error encoding at a loop filter; and
controlling a digitally controller oscillator (DCO) with the loop filter to generate a reference frequency output.
15 . The method of claim 14 , further comprising:
generating the feedback signal by applying a multimodulus divider (MMD) to the reference frequency output.
16 . The method of claim 15 , further comprising:
dithering the multiple bit error encoding to interface the fine resolution encoder to the MMD.
17 . The method of claim 14 , further comprising configuring an analog to digital converter (ADC) to act in a fine resolution mode to provide the fine resolution encoder that generates the multiple bit error encoding.
18 . The method of claim 17 , further comprising configuring the ADC to act in a coarse resolution mode for acquisition of frequency lock.
19 . A phase locked loop (PLL) comprising:
a reference frequency input;
a phase and frequency detector charge pump in communication with the reference frequency input;
a delta signal analog to digital converter (ADC) driven by the charge pump, the ADC comprising a resolution mode input configured to selectively change the ADC between:
a fine resolution mode providing a fine mode number of quantization levels for phase and frequency error; and
a coarse resolution mode providing fewer quantization levels for the phase and frequency error than the fine mode number of quantization levels;
a loop filter following the ADC and configured to accept the phase and frequency error and responsively drive a digitally controlled oscillator (DCO) that generates a reference frequency output; and
a feedback path from the DCO to the charge pump, the feedback path comprising a multimodulus divider (MMD).
20 . The PLL of claim 19 , further comprising a dither circuit configured to interface the fine mode number of quantization levels to a lower-resolution MMD control grid of the MMD.