IP Library Granted Patent US 9,047,205
Granted Patent B1
US 9,047,205 · App. 13/968,323 · Granted Jun 2, 2015

Data storage device employing orthogonal equalization and sequence detection to compensate for two-dimensional intersymbol interference

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Quick Facts
Patent No.
US 9,047,205
App. No.
13/968,323
Granted
Jun 2, 2015
Kind
B1
Abstract

A data storage device is disclosed comprising a non-volatile memory (NVM), wherein data is read from the NVM to generate a two dimension matrix of signal samples, including a first dimension and a second dimension. The matrix of signal samples is first equalized to reduce intersymbol interference (ISI) in the first dimension to generate second dimension signal samples, and second equalized to reduce ISI in the second dimension to generate first dimension signal samples. A first data sequence is detected in response to the first dimension signal samples, and a second data sequence is detected in response to the second dimension signal samples.

Claims (53)

1. A data storage device comprising:

a non-volatile memory (NVM); and

control circuitry operable to:

read data from the NVM to generate a two dimension matrix of signal samples, including a first dimension and a second dimension;

first equalize the matrix of signal samples to reduce intersymbol interference (ISI) in the first dimension to generate second dimension signal samples;

second equalize the matrix of signal samples to reduce ISI in the second dimension to generate first dimension signal samples;

first detect a first data sequence in response to the first dimension signal samples;

second detect a second data sequence in response to the second dimension signal samples;

wherein the control circuitry is further operable to:

compare the first data sequence to the second data sequence;

generate at least one erasure pointer corresponding to when the first data sequence does not match the second data sequence; and

process the at least one erasure pointer to correct at least one error in at least one of the first data sequence and the second data sequence.

2. The data storage device as recited in claim 1 , wherein the control circuitry is further operable to:

generate first reliability metrics when detecting the first data sequence; and

process the first reliability metrics when second detecting the second data sequence.

3. The data storage device as recited in claim 2 , wherein the control circuitry is further operable to:

generate second reliability metrics when detecting the second data sequence; and

process the second reliability metrics when first detecting the first data sequence.

4. The data storage device as recited in claim 3 , wherein the control circuitry is further operable to iterate the first detecting and the second detecting at least once.

5. The data storage device as recited in claim 4 , wherein the control circuitry is further operable to iterate the first detecting and the second detecting until the first data sequence matches the second data sequence.

6. The data storage device as recited in claim 2 , wherein the control circuitry is operable to second detect the second data sequence using a binary trellis sequence detector.

7. The data storage device as recited in claim 3 , wherein the control circuitry is operable to first detect the first data sequence using a first binary trellis sequence detector and second detect the second data sequence using a second binary trellis sequence detector.

8. The data storage device as recited in claim 1 , wherein the NVM comprises a non-volatile semiconductor memory.

9. The data storage device as recited in claim 1 , wherein the NVM comprises a disk of a disk drive.

10. The data storage device as recited in claim 9 , wherein:

the disk comprises a plurality of data tracks;

the first dimension corresponds to signal samples of multiple data tracks across a radius of the disk; and

the second dimension corresponds to signal samples of a data track along a circumference of the disk.

11. A method of operating a data storage device comprising a non-volatile memory (NVM), the method comprising:

reading data from the NVM to generate a two dimension matrix of signal samples, including a first dimension and a second dimension;

first equalizing the matrix of signal samples to reduce intersymbol interference (ISI) in the first dimension to generate second dimension signal samples;

second equalizing the matrix of signal samples to reduce ISI in the second dimension to generate first dimension signal samples;

first detecting a first data sequence in response to the first dimension signal samples;

second detecting a second data sequence in response to the second dimension signal samples;

comparing the first data sequence to the second data sequence;

generating at least one erasure pointer corresponding to when the first data sequence does not match the second data sequence; and

processing the at least one erasure pointer to correct at least one error in at least one of the first data sequence and the second data sequence.

12. The method as recited in claim 11 , further comprising:

generating first reliability metrics when detecting the first data sequence; and

processing the first reliability metrics when second detecting the second data sequence.

13. The method as recited in claim 12 , further comprising:

generating second reliability metrics when detecting the second data sequence; and

processing the second reliability metrics when first detecting the first data sequence.

14. The method as recited in claim 13 , further comprising iterating the first detecting and the second detecting at least once.

15. The method as recited in claim 14 , further comprising iterating the first detecting and the second detecting until the first data sequence matches the second data sequence.

16. The method as recited in claim 12 , further comprising second detecting the second data sequence using a binary trellis sequence detector.

17. The method as recited in claim 13 , further comprising first detecting the first data sequence using a first binary trellis sequence detector and second detecting the second data sequence using a second binary trellis sequence detector.

18. The method as recited in claim 11 , wherein the NVM comprises a non-volatile semiconductor memory.

19. The method as recited in claim 11 , wherein the NVM comprises a disk of a disk drive.

20. The method as recited in claim 19 , wherein:

the disk comprises a plurality of data tracks;

the first dimension corresponds to signal samples of multiple data tracks across a radius of the disk; and

the second dimension corresponds to signal samples of a data track along a circumference of the disk.

Assignments (8)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2013
From: CHEN, YIMING; KRISHNAN, ANANTHA RAMAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 031079/0820 →