Hardware accelerator configuration by a translation of configuration data
View Patent ↗A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data. The configuration controller may transmit each set of configuration data to the corresponding configurable math hardware accelerator and write the configuration data to configuration registers of the math hardware accelerator.
1. An apparatus comprising:
a microprocessor core;
a hardware accelerator including a configuration register and configurable by contents of the configuration register to apply a predetermined signal processing function upon input operand data; and
a configuration controller comprising a predetermined data-structure specification and a configuration model, the predetermined data-structure specification including one or more data structures, the configuration model including one or more structural details of the configuration register, and the configuration controller being responsive to a notification from the microprocessor core to configure the contents of the configuration register of the hardware accelerator by a translation of configuration data from a first format associated with the predetermined data-structure specification to a second format associated with the configuration model.
2. The apparatus of claim 1 , wherein the configuration controller comprises a pointer register for a data pointer indicating a location of the configuration data in memory.
3. The apparatus of claim 1 , wherein the notification from the microprocessor core includes a data pointer indicating a location of the configuration data in memory.
4. The apparatus of claim 1 , wherein the hardware accelerator is configured to apply a part of a predetermined signal processing method upon the input operand data.
5. The apparatus of claim 1 , wherein the configuration controller is further configured to transfer the input operand data from memory to an input data register of the hardware accelerator.
6. The apparatus of claim 1 , wherein the hardware accelerator is further configured to transfer the input operand data from memory to an input data register of the hardware accelerator.
7. An integrated semiconductor die comprising the apparatus of claim 1 .
8. The apparatus of claim 1 , wherein the hardware accelerator is configured to select the predetermined signal processing function from a group of fast Fourier transform (FFT), inverse FFT (iFFT), vector*matrix multiplication, finite impulse response (FIR) filter, infinite impulse response (IIR) filter, logarithm, and square root.
9. The apparatus of claim 1 , wherein
the notification from the microprocessor core identifies the configuration data at a location in memory, the configuration data being structured at the location in memory in the first format in accordance with the predetermined data-structure specification; and
the configuration controller is configured to fetch the configuration data in the first format from the memory.
10. The apparatus of claim 9 , wherein the configuration controller is configured to perform operations including:
translating the configuration data in the first format into register-level configuration data in the second format in accordance with the predetermined data-structure specification and the configuration model; and
transferring the register-level configuration data to the configuration register of the hardware accelerator.
11. The apparatus of claim 1 , wherein the apparatus comprises a plurality of hardware accelerators, each hardware accelerator of the plurality of hardware accelerators including a corresponding configuration register and being configurable by contents of the corresponding configuration register to apply a corresponding predetermined signal processing function upon input operand data; and
the configuration controller is configured to select the hardware accelerator from the plurality of hardware accelerators in accordance with the notification from the microprocessor core.
12. The apparatus of claim 1 , wherein the configuration model is based on an architecture of the configuration register.
13. The apparatus of claim 1 , wherein
the one or more data structures include high-level-language data structures; and
and the one or more structural details include register addresses and register sizes.
14. A method, comprising:
responsive to a notification from a microprocessor core, configuring, by a configuration controller comprising a predetermined data-structure specification and a configuration model, contents of a configuration register included in a hardware accelerator, the predetermined data-structure specification including one or more data structures, the configuration model including one or more structural details of the configuration register, and the contents of the configuration register being configured by a translation of configuration data from a first format associated with the predetermined data-structure specification to a second format associated with the configuration model; and
performing, by the hardware accelerator, a processing operation on input operand data, wherein operation of the hardware accelerator is determined by the contents of the configuration register.
15. The method of claim 14 , wherein the configuration data is identified by a data pointer included in the notification and indicating a location of the configuration data in memory.
16. The method of claim 14 , further comprising:
compiling source code comprising high-level language declarations of the predetermined data-structure specification to generate the configuration data in the first format; and
loading the configuration data into respective predetermined address spaces of memory.
17. The method of claim 14 , further comprising:
identifying the configuration data at a location in memory, the configuration data being structured at the location in memory in the first format in accordance with the predetermined data-structure specification; and
fetching, by the configuration controller, the configuration data in the first format from the memory.
18. The method of claim 17 , comprising:
translating, by the configuration controller, the configuration data in the first format into register-level configuration data in the second format in accordance with the predetermined data-structure specification and the configuration model; and
transferring, by the configuration controller, the register-level configuration data to the configuration register of the hardware accelerator.
19. The method of claim 14 , wherein the configuration data is identified by a data pointer included in a pointer register of the configuration controller and indicating a location of the configuration data in memory.
20. An apparatus comprising:
a microprocessor core;
a hardware accelerator including a configuration register and configurable by contents of the configuration register to apply a predetermined signal processing function upon input operand data; and
means for configuring the contents of the configuration register of the hardware accelerator in response to a notification from the microprocessor core, the contents of the configuration register being configured by a translation of configuration data from a first format associated with a predetermined data-structure specification that includes one or more data structures to a second format associated with a configuration model that includes one or more structural details of the configuration register.