IP Library Granted Patent US 9,425,050
Granted Patent B2
US 9,425,050 · App. 13/969,773 · Granted Aug 23, 2016

System and method for providing an electron blocking layer with doping control

Inventors: Joseph M. Freund (Fogelsville, PA); John M. DeLucca (Wayne, PA)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
H01L21/2205H01L21/0242H01L21/0254H01L21/02458H01L21/02488H01L21/02507H01L21/02513H01L21/02576H01L21/02579H01L33/145
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Quick Facts
Patent No.
US 9,425,050
App. No.
13/969,773
Granted
Aug 23, 2016
Kind
B2
Abstract

Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.

Claims (44)

1. A semiconductor assembly, comprising:

a base substrate;

a layer stack formed upon the base substrate; and

an electron blocking layer formed upon the layer stack,

wherein the electron blocking layer includes a magnesium-doped layer as well as a lithium aluminate layer sandwiched between the magnesium-doped layer and the layer stack so as to promote reduced diffusion of magnesium into the layer stack.

2. The semiconductor assembly as claimed in claim 1 , wherein the base substrate is a lithium aluminate substrate.

3. The semiconductor assembly as claimed in claim 1 , wherein the layer stack includes a cladding layer, the cladding layer being formed upon the base substrate.

4. The semiconductor assembly as claimed in claim 3 , wherein the layer stack includes one or more barrier layers, a first barrier layer included in the one or more barrier layers being formed upon the cladding layer.

5. The semiconductor assembly as claimed in claim 4 , wherein the layer stack includes one or more quantum well layers, a quantum well layer included in the one or more quantum well layers being formed upon the first barrier layer.

6. The semiconductor assembly as claimed in claim 5 , wherein the lithium aluminate layer is patterned.

7. The semiconductor assembly as claimed in claim 5 , wherein the lithium aluminate layer is formed directly upon a second barrier layer included in the one or more barrier layers, the second barrier layer being formed upon the quantum well layer.

8. The semiconductor assembly as claimed in claim 6 , wherein the patterned lithium aluminate layer is formed upon an aluminum nitride layer, the aluminum nitride layer being formed upon a second barrier layer included in the one or more barrier layers, the second barrier layer being formed upon the quantum well layer.

9. The semiconductor assembly as claimed in claim 6 , wherein the patterned lithium aluminate layer forms multiple rows of interleaved islands.

10. The semiconductor assembly as claimed in claim 9 , wherein the patterned lithium aluminate layer is formed upon an aluminum nitride layer, the aluminum nitride layer being formed upon a second barrier layer included in the one or more barrier layers, the second barrier layer being formed upon the quantum well layer.

11. The semiconductor assembly as claimed in claim 5 , wherein a gallium nitride layer is formed upon the electron blocking layer.

12. The semiconductor assembly as claimed in claim 1 , wherein the layer stack is an active layer of the semiconductor assembly configured to provide light emission.

13. A semiconductor assembly, comprising:

a layer stack, the layer stack including a substrate and a cladding layer, the cladding layer being formed upon the substrate, the layer stack further including one or more barrier layers, a first barrier layer included in the one or more barrier layers being formed upon the cladding layer, the layer stack including one or more quantum well layers, a quantum well layer included in the one or more quantum well layers being formed upon the first barrier layer; and

an electron blocking layer formed upon the layer stack,

wherein the layer stack is an active layer of the semiconductor assembly configured to provide light emission, and wherein the electron blocking layer includes a magnesium-doped layer as well as a lithium aluminate layer positioned between and separating the magnesium-doped layer from the layer stack thereby promoting reduced diffusion of magnesium into the layer stack, the lithium aluminate layer being formed upon an aluminum gallium nitride layer, the aluminum gallium nitride layer being formed upon a second barrier layer included in the one or more barrier layers, the second barrier layer being formed upon the quantum well layer.

14. The semiconductor assembly as claimed in claim 13 , wherein the substrate is a lithium aluminate substrate.

15. The semiconductor assembly as claimed in claim 14 , wherein the cladding layer is a silicon-doped gallium nitride cladding layer.

16. The semiconductor assembly as claimed in claim 15 , wherein the one or more barrier layers are silicon-doped gallium nitride barrier layers.

17. The semiconductor assembly as claimed in claim 16 , wherein the one or more quantum well layers are silicon-doped indium gallium nitride quantum well layers.

18. The semiconductor assembly as claimed in claim 17 , wherein the magnesium-doped layer is a magnesium-doped aluminum gallium nitride electron blocking layer.

19. A method of producing a semiconductor assembly, comprising:

forming a base substrate;

forming a layer stack upon the base substrate; and

forming an electron blocking layer upon the layer stack,

wherein the electron blocking layer includes a magnesium-doped layer and a lithium aluminate layer, wherein the lithium aluminate layer is in direct contact with at least some of the magnesium-doped layer and provides a physical separation between the magnesium-doped layer and the layer stack thereby at least partially inhibiting diffusion of magnesium into the layer stack.

20. The method as claimed in claim 19 , wherein the step of forming a layer stack comprises:

forming a cladding layer upon the base substrate;

forming a first barrier layer upon the cladding layer;

forming a first quantum well layer upon the first barrier layer; and

forming a second barrier layer upon the first well layer.

21. An apparatus, comprising:

a housing; and

a semiconductor assembly at least substantially contained within the housing of the apparatus, the semiconductor assembly including:

a base substrate;

a layer stack formed upon the base substrate; and

an electron blocking layer formed upon the layer stack,

wherein the electron blocking layer includes magnesium-doped portion as well as a lithium aluminate layer that promotes reduced diffusion of magnesium into the layer stack by virtue of being positioned between the magnesium-doped portion and the layer stack.

22. The apparatus as claimed in claim 21 , wherein the apparatus is one of:

an automobile, an optical disk playback product, a lighting fixture, a laptop, a mobile phone, a digital television, or a camera.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2013
From: FREUND, JOSEPH M.; DELUCCA, JOHN M.
To: LSI CORPORATION
Reel/Frame 031035/0353 →
Continuity (2)
Provisional Application 61866588 · Aug 16, 2013
Related Publication 20150048310A1 · Feb 19, 2015