Adaptive modal PAM2/PAM4 in-phase (I) quadrature (Q) phase detector for a receiver
View Patent ↗A phase detector includes data detection logic for detecting data in a communication signal, amplitude detection logic for processing modulation chosen from any of a PAM2 and a PAM4 communication modality, in-phase edge detection logic for detecting in-phase edge information in the communication signal, quadrature edge detection logic for detecting quadrature edge information in the communication signal, and mixing logic for determining an amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel.
1. A phase detector, comprising:
data detection logic for detecting data in a communication signal;
amplitude detection logic for processing modulation of a PAM2 and a PAM4 communication modality;
in-phase edge detection logic for detecting in-phase edge information in the communication signal;
quadrature edge detection logic for detecting quadrature edge information in the communication signal substantially simultaneous with the detection of the in-phase edge information; and
mixing logic for determining a variable amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel.
2. The phase detector of claim 1 , wherein the data detection logic comprises data sampler logic configured to generate a digital data signal.
3. The phase detector of claim 2 , wherein the in-phase edge detection logic comprises in-phase sampler logic configured to generate a digital in-phase edge signal.
4. The phase detector of claim 2 , wherein the quadrature edge detection logic comprises quadrature sampler logic configured to generate a digital quadrature edge signal.
5. The phase detector of claim 2 , wherein the mixing logic determines an amount of in-phase edge information and quadrature edge information to be applied based on channel loss.
6. The phase detector of claim 5 , wherein the channel loss is determined by bit error rate.
7. The phase detector of claim 5 , wherein the channel loss is determined by clock jitter.
8. The phase detector of claim 4 , further comprising majority vote logic configured to apply the in-phase edge information and quadrature edge information provided by the mixing logic to develop a clock adjustment signal.
9. A method for processing a signal in a phase detector, comprising:
detecting data in a communication signal;
enabling amplitude detection of the communication signal regardless of whether the communication signal comprises a corresponding PAM2 or PAM4 communication modality;
substantially simultaneously detecting in-phase edge information in the communication signal and quadrature edge information in the communication signal; and
determining a variable amount of in-phase edge information and quadrature edge information to be applied to the communication signal based on at least one channel parameter in the communication channel.
10. The method of claim 9 , wherein detecting data comprises using a data sampler logic configured to generate a digital data signal.
11. The method of claim 10 , wherein detecting the in-phase edge information comprises using in-phase sampler logic configured to generate a digital in-phase edge signal.
12. The method of claim 10 , wherein detecting the quadrature edge information comprises using quadrature sampler logic configured to generate a digital quadrature edge signal.
13. The method of claim 10 , wherein the at least one channel parameter is channel loss.
14. The method of claim 13 , wherein the channel loss is determined by analyzing bit error rate.
15. The method of claim 13 , wherein the channel loss is determined by analyzing clock jitter.
16. The method of claim 12 , further comprising applying the in-phase edge information and quadrature edge information to develop a clock adjustment signal.
17. A receiver system, comprising:
a linear equalizer configured to provide a communication signal to a feed forward equalizer (FFE) and a decision feedback equalizer (DFE);
data detection logic for detecting data in the communication signal;
amplitude detection logic for processing modulation of a PAM2 and a PAM4 communication modality;
in-phase edge detection logic for detecting in-phase edge information in the communication signal;
quadrature edge detection logic for detecting quadrature edge information in the communication signal substantially simultaneous with the detection of the in-phase edge information; and
mixing logic for determining a variable amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel.
18. The receiver system of claim 17 , wherein the data detection logic comprises data sampler logic configured to generate a digital data signal.
19. The receiver system of claim 18 , wherein the in-phase edge detection logic comprises in-phase sampler logic configured to generate a digital in-phase edge signal.
20. The receiver system of claim 18 , wherein the quadrature edge detection logic comprises quadrature sampler logic configured to generate a digital quadrature edge signal.
21. The receiver system of claim 18 , wherein the mixing logic determines an amount of in-phase edge information and quadrature edge information to be applied based on channel loss.
22. The receiver system of claim 21 , wherein the channel loss is determined by bit error rate.
23. The receiver system of claim 21 , wherein the channel loss is determined by clock jitter.
24. The receiver system of claim 20 , further comprising majority vote logic configured to apply the in-phase edge information and quadrature edge information provided by the mixing logic to develop a clock adjustment signal.