Semiconductor memory device and method for testing same
View Patent ↗A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122 , and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.
1. A semiconductor memory device test method, the device comprising:
a plurality of data input/output terminals; and
a memory cell array in which one address is composed of multiple bits that can be read/written in parallel with the plurality of data input/output terminals,
wherein the device further comprises a test mode in which data read in parallel from the multiple-bit memory cell array to the plurality of data input/output terminals is written in parallel in multiple bits of an address different from the read address, and
wherein the test is conducted by writing first and second data in first and second regions, respectively, in the memory cell array in advance, using the test mode, writing the second data read from the second region in the first region, and reading the data from the first region after the second data is written in the first region.
2. The semiconductor memory device test method according to claim 1 , the device further comprising, assuming that the above test mode is a first test mode, a second test mode in which part of the plurality of data input/output terminals, the number of which is smaller than the number of bits of the memory cell array, is used to write data in the multiple bits of the memory cell array in parallel and read the multiple-bit data from the multiple bits in parallel, wherein writing first and second data in first and second region, respectively, in the memory cell array in advance and reading data from the first region are implemented with the second test mode.
3. The semiconductor memory device test method according to claim 2 , wherein, after the test in which data is read from the first region, the second data is written in the first region with the second test mode, the first data is written in the second region with the second test mode, the first data read from the first region is written in the second region with the first test mode, and a read test is conducted on the second region with the second test mode.
4. The semiconductor memory device test method according to claim 3 , wherein the semiconductor memory device comprises, in the first test mode, a function of writing by a burst operation data read by a burst operation from the memory cell array in a region having an initial address different from the address read by the burst operation, wherein writing the second data read from the second region in the first region with the first test mode and writing the first data read from the first region in the second region with the first test mode are implemented with the function of burst reading and burst writing.