Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.
1. A semiconductor device, comprising:
a first wiring layer including a first interlayer insulating layer, and a first wiring embedded in the first interlayer insulating layer;
a second wiring layer including a cap insulating layer formed over the first wiring layer, a second interlayer insulating layer provided over the cap insulating layer, and a second wiring embedded in the second interlayer insulating layer;
a first transistor of a first conductive type provided in the first wiring layer and the second wiring layer;
a second transistor of a second conductive type other than the first conductive type provided in the first wiring layer and the second wiring layer,
wherein the first transistor includes:
a first gate electrode as one first wiring;
a first gate insulating film provided over the first gate electrode and including a part of the cap insulating layer;
a first oxide semiconductor layer formed over the first gate insulating film;
a first hard mask layer provided over the first oxide semiconductor layer; and
a first insulating sidewall film covering a side of the first oxide semiconductor layer,
wherein the second transistor includes:
a second gate electrode as another first wiring;
a second gate insulating film provided over the second gate electrode to lead to the first gate insulating film, and including another part of the cap insulating layer;
a second oxide semiconductor layer provided over the second gate insulating film; and
a second hard mask layer provided over the second oxide semiconductor layer.
2. The semiconductor device according to claim 1 , wherein the second gate insulating film is thinner than the first gate insulating film.
3. The semiconductor device according to claim 1 , wherein the second gate insulating film includes:
a second lower gate insulating film leading to the first gate insulating film; and
a second upper gate insulating film provided over the second lower gate insulating film.
4. The semiconductor device according to claim 3 , wherein a total thickness of the second lower gate insulating film and the second upper gate insulating film is equal to that of the first gate insulating film.
5. The semiconductor device according to claim 1 , wherein the first gate insulating film includes:
a first lower gate insulating film leading to the second gate insulating film; and
a first upper gate insulating film provided over the first lower gate insulating film.
6. The semiconductor device according to claim 5 , wherein the second gate insulating film includes:
a second lower gate insulating film leading to the first gate insulating film; and
a second upper gate insulating film provided over the second lower gate insulating film.
7. The semiconductor device according to claim 5 , wherein the first sidewall film further covers a side of the first upper gate insulating film.
8. The semiconductor device according to claim 1 , wherein the second transistor is provided separately from the second interlayer insulating layer, and
wherein the second transistor further includes a second insulating sidewall film covering the sides of the second oxide semiconductor layer and the second hard mask layer.
9. The semiconductor device according to claim 1 ,
wherein one of the first transistor and the second transistor is a P-type transistor forming a CMOS, and
wherein the other of the first transistor and the second transistor is an N-type transistor forming the CMOS, and
wherein the P-type transistor and the N-type transistor differ in material or property of a source/drain electrode.
10. The semiconductor device according to claim 9 , wherein the source/drain electrode of the P-type transistor has a contacting part in contact with a P-type oxide semiconductor layer which is one of the first oxide semiconductor layer and the second oxide semiconductor layer, the contacting part containing a conductive oxide or another P-type oxide semiconductor.
11. The semiconductor device according to claim 10 , wherein the contacting part contains at least one material selected from the group comprised of ruthenium oxide, tin-doped indium oxide, and titanium oxide.
12. The semiconductor device according to claim 9 , wherein the source/drain electrode of the P-type transistor has a contacting part in contact with a P-type oxide semiconductor layer which is one of the first oxide semiconductor layer and the second oxide semiconductor layer, said contacting part containing metal for forming an interface layer by partially modifying at least one of the oxide semiconductor layer and the source/drain electrode.
13. The semiconductor device according to claim 12 , wherein the contacting part contains a titanium oxide.
14. The semiconductor device according to claim 13 , wherein the source/drain electrode of the N-type transistor has a contacting part in contact with an N-type oxide semiconductor layer which is one of the first oxide semiconductor layer and the second oxide semiconductor layer, said contacting part containing titanium.