IP Library Granted Patent US 9,202,577
Granted Patent B2
US 9,202,577 · App. 13/976,002 · Granted Dec 1, 2015

Solid state drive management in power loss recovery

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Quick Facts
Patent No.
US 9,202,577
App. No.
13/976,002
Granted
Dec 1, 2015
Kind
B2
Abstract

Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. Other embodiments may be described and/or claimed.

Claims (49)

1. An apparatus comprising:

a memory controller configured to defragment a non-volatile memory by being configured to:

write valid data from a first erase block into a page of a second erase block;

determine whether the valid data is associated with a secured state in the page;

erase the first erase block based on a determination that the valid data is associated with the secured state;

determine whether the page of the second erase block is a lower page; and

determine whether the valid data is associated with an unsecured state based on a determination that the page is the lower page.

2. The apparatus of claim 1 , wherein the memory controller is further configured to determine whether the valid data is associated with the secured state by being configured to:

determine whether data is successfully written to an upper page that corresponds to the lower page.

3. The apparatus of claim 2 , wherein the valid data corresponds to a logical block address (LBA).

4. The apparatus of claim 2 , wherein the memory controller is further configured to:

store a location stamp associated with the lower page based on write of the valid data into the lower page; and

identify the upper page based on the location stamp.

5. The apparatus of claim 2 , wherein the memory controller is further configured to schedule an erase operation in a deferred erase queue until determination that the upper page is written successfully.

6. The apparatus of claim 2 , wherein the memory controller is further configured to:

receive a flush command after a write of the valid data into the lower page;

write pad data to an upper page; and

return a flush-complete message after the write of the pad data to the upper page.

7. The apparatus of claim 1 , wherein the memory controller is further configured to:

monitor writes to an upper page of the second erase block; and

determine whether the valid data is associated with the secured state based on monitored writes.

8. The apparatus of claim 1 , further comprising:

a host configured to issue a plurality of memory access requests to the memory controller.

9. The apparatus of claim 1 , wherein the apparatus comprises a solid-state drive having the non-volatile memory.

10. The apparatus of claim 1 , further comprising:

a wireless interface configured to wirelessly couple the apparatus to a radio access network.

11. The apparatus of claim 10 , comprising: a mobile computing device having the non-volatile memory and the memory controller.

12. One or more non-transitory computer-readable media having instructions stored thereon that, if executed by one or more processors, cause a device to:

write data from a first erase block to a lower page within a second erase block;

monitor writes to an upper page within the second erase block;

schedule an erase of the first erase block based on monitored writes;

schedule the erase of the first erase block based on completion of a write to the upper page;

associate the data with an unsecured state based on said write of data to the lower page; and

after said association of the data with the unsecured state, associate the data with a secured state based on said monitor of writes to the upper page.

13. The one or more non-transitory computer-readable media of claim 12 , wherein the data is written to a first location in the lower page and the instructions, if executed, further cause the device to:

schedule an erase operation in a deferred erase queue until a determination that a write to the upper page is successfully completed.

14. A method, comprising:

detecting a power loss event related to a solid-state drive (SSD);

accessing saved context information based on detected power-loss event;

restoring a logical-to-physical (L2P) indirection table based on the saved context information; and

updating the L2P indirection table based on a plurality of writes to a non-volatile memory (NVM) of the SSD that occurred subsequent to a saving of the context information;

determining whether a number of errors associated with the updating is greater than a predetermined threshold that is greater than one; and

ceasing the updating based on a determination that a number of errors associated with the updating is greater than a predetermined threshold.

15. The method of claim 14 , further comprising:

checking an error correction code (ECC) associated with individual writes of the plurality of writes to determine whether the individual writes are associated with an error.

16. The method of claim 14 , wherein the plurality of writes include a plurality of page writes.

17. The method of claim 14 , wherein the predetermined threshold is a number of consecutive errors.

18. The method of claim 14 , wherein the predetermined threshold is a number of page errors.

19. One or more non-transitory computer-readable media having instructions stored thereon that, if executed by one or more processors, cause a device to perform a method in accordance with claim 14 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 062437/0255 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2014
From: MANGOLD, RICHARD P.; COULSON, RICHARD L.; ROYER, ROBERT J., JR.; TRIKA, SANJEEV N.
To: INTEL CORPORATION
Reel/Frame 033647/0724 →