Optimized cold boot for non-volatile memory
Various embodiments are directed to apparatuses and methods for faster solid state drive (SSD) boot-up. On boot-up, SSD control algorithms may load non-logical to physical (L2P) parts of a context and signal the system that the SSD is ready. The context may comprise various state data pertaining to the SSD. After signaling that the SSD may be ready to receive access requests, the SSD control algorithms may begin loading segments of the L2P table sequentially. Access to the L2P table may be blocked, however, when a requested segment has not yet been loaded. In such cases, the SSD control algorithms may then load the requested segment out of turn and then service the access request.
1. An apparatus, comprising:
a processor circuit executing solid state drive (SSD) control algorithms operative to:
cycle power to a solid state drive (SSD), the SSD including a logical-to-physical (L2P) table stored to a non-volatile memory at the SSD, the L2P table comprising an address mapping schema for translating logical block addresses (LBAs) to physical addresses in the SSD, the L2P table being partitioned into multiple table segments, each of the multiple table segments including a sequential grouping of LBAs;
perform a partial boot-up for the SSD, the partial boot-up not including loading of the L2P table to a volatile memory maintained at the SSD;
signal that the SSD is ready to process access requests upon completion of the partial boot-up;
load the multiple table segments of the L2P table in a sequential manner to the volatile memory; and
handle an access request specifying an LBA within an unloaded segment.
2. The apparatus of claim 1 , the processor circuit operative to:
load the unloaded segment of the L2P table to the volatile memory; and
resume the loading of the multiple table segments of the L2P table in the sequential manner once the unloaded segment has been loaded to the volatile memory.
3. The apparatus of claim 2 , the processor circuit operative to load multiple additional unloaded segments of the L2P table to the volatile memory, the multiple additional unloaded segments being consecutive to the unloaded segment.
4. The apparatus of claim 2 , the processor circuit operative to determine the segment associated with an LBA by taking an integer value after dividing the requested LBA by a number of LBAs per segment, where the LBAs are sequentially numbered from 1 to n.
5. The apparatus of claim 2 , comprising the processor circuit operative to:
determine whether a particular segment has been loaded to the volatile memory prior to loading the particular segment to the volatile memory;
receive an access request, the access request including an LBA;
verify the segment associated with the LBA in the access request has been loaded to the volatile memory; and
service the access request for a particular segment upon verification the segment has been loaded to the volatile memory.
6. The apparatus of claim 1 , the processor circuit operative to power down the SSD when the processor circuit determines an idle state for the SSD.
7. The apparatus of claim 6 , the processor circuit operative to power up the SSD when the processor circuit determines the SSD is needed.
8. The apparatus of claim 1 , the SSD operative to signal the processor circuit to power the SSD down when the SSD determines it is in an idle state.
9. The apparatus of claim 1 , the processor circuit implemented as firmware on an embedded processor within the SSD.
10. The apparatus of claim 1 , the processor circuit implemented as hardware state machines within the SSD.
11. The apparatus of claim 1 , wherein the processor circuit executes the SSD control algorithms.
12. A method, comprising:
powering on a solid state drive (SSD);
performing a partial boot-up for the SSD, the partial boot-up not including loading of a logical-to-physical (L2P) table for the SSD to a volatile memory at the SSD, the L2P table stored to a non-volatile memory at the SSD, the L2P table comprising an address mapping schema for translating logical block addresses (LBAs) to physical addresses in the SSD, the L2P table being partitioned into multiple table segments, each of the multiple table segments including a sequential grouping of LBAs;
signaling that the SSD is ready to process access requests upon completion of the partial boot-up;
loading the multiple table segments of the L2P table in a sequential manner to the volatile memory; and
interrupting the sequential loading of the multiple table segments of the L2P table to handle an access request specifying an LBA within an unloaded segment.
13. The method of claim 12 comprising:
loading the unloaded segment of the L2P table to the volatile memory; and
resuming the loading of the multiple table segments of the L2P table in the sequential manner once the unloaded segment has been loaded to the volatile memory.
14. The method of claim 13 comprising loading multiple additional unloaded segments of the L2P table to the volatile memory, the multiple additional unloaded segments being consecutive to the unloaded segment.
15. The method of claim 12 comprising determining the unloaded segment associated with an access request specifying an LBA by taking an integer value after dividing the requested LBA by a number of LBAs per segment, where the LBAs are sequentially numbered from 1 to n.
16. The method of claim 12 comprising:
determining whether a particular segment has been loaded to the volatile memory prior to loading the particular segment to the volatile memory;
receiving an access request, the access request including an LBA;
verifying the segment associated with the LBA in the access request has been loaded to the volatile memory; and
servicing the access request for a particular segment upon verification the segment has been loaded to the volatile memory.
17. A system, comprising:
a processor communicatively coupled with additional system components and operative to execute software programs;
a solid state drive (SSD), the SSD including a logical-to-physical (L2P) table stored to a non-volatile memory at the SSD, the L2P table comprising an address mapping schema for translating logical block addresses (LBAs) to physical addresses in the SSD, the L2P table being partitioned into multiple table segments, each of the multiple table segments including a sequential grouping of LBAs; and
a processor circuit executing solid state drive (SSD) control algorithms operative to:
cycle power to the SSD;
perform a partial boot-up for the SSD, the partial boot-up not including loading of the L2P table to a volatile memory;
signal that the SSD is ready to process access requests upon completion of the partial boot-up;
load the multiple table segments of the L2P table in a sequential manner to the volatile memory; and
handle an access request specifying an LBA within an unloaded segment.
18. The system of claim 17 , the processor circuit operative to:
load the unloaded segment of the L2P table to the volatile memory; and
resume the loading of the multiple table segments of the L2P table in the sequential manner once the unloaded segment has been loaded to the volatile memory.
19. The system of claim 18 , the processor circuit operative to load multiple additional unloaded segments of the L2P table to the volatile memory, the multiple additional unloaded segments being consecutive to the unloaded segment.
20. The system of claim 18 , the processor circuit operative to determine the segment associated with an LBA by taking an integer value after dividing the requested LBA by a number of LBAs per segment, where the LBAs are sequentially numbered from 1 to n.
21. The system of claim 18 , comprising the processor circuit operative to:
determine whether a particular segment has been loaded to the volatile memory prior to loading the particular segment to the volatile memory;
receive an access request, the access request including an LBA;
verify the segment associated with the LBA in the access request has been loaded; and
service the access request for a particular segment upon verification the segment has been loaded to the volatile memory.
22. The system of claim 17 , the SSD operative to signal the processor circuit to power the SSD down when the SSD determines it is in an idle state.
23. The system of claim 17 , the processor circuit operative to power up the SSD when the processor determines the SSD is needed.
24. The system of claim 17 , the processor circuit implemented as firmware on an embedded processor within the SSD.
25. The system of claim 17 , the processor circuit implemented as hardware state machines within the SSD.
26. At least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a system to:
perform a partial boot-up for an SSD, the partial boot-up not including loading of a logical-to-physical (L2P) table for the SSD to a volatile memory at the SSD, the L2P table stored to a non-volatile memory at the SSD, the L2P table comprising an address mapping schema for translating logical block addresses (LBAs) to physical addresses in the SSD, the L2P table being partitioned into multiple table segments, each of the multiple table segments including a sequential grouping of LBAs;
signal that the SSD is ready to process access requests upon completion of the partial boot-up;
load the multiple table segments of the L2P table in a sequential manner to the volatile memory; and
load an unloaded segment of the L2P table to the volatile memory when an access request specifying an LBA within the unloaded segment is received.
27. The non-transitory computer-readable storage medium of claim 26 , containing instructions that when executed cause a system to resume the loading of the multiple table segments of the L2P table in the sequential manner once the unloaded segment has been loaded to the volatile memory and load multiple additional unloaded segments of the L2P table to the volatile memory, the multiple additional unloaded segments being consecutive to the unloaded segment.
28. The non-transitory computer-readable storage medium of claim 26 , containing instructions that when executed cause a system to determine the segment associated with an LBA by taking an integer value after dividing the requested LBA by a number of LBAs per segment, where the LBAs are sequentially numbered from 1 to n.
29. The non-transitory computer-readable storage medium of claim 26 , containing instructions that when executed cause a system to:
determine whether a particular segment has been loaded to the volatile memory prior to loading the particular segment to the volatile memory;
receive an access request, the access request including an LBA;
verify the segment associated with the LBA in the access request has been loaded to the volatile memory; and
service the access request for a particular segment upon verification the segment has been loaded to the volatile memory.