Driving method of variable resistance element and non-volatile memory device

1. A method of driving a variable resistance element including a first electrode, a second electrode, and a metal oxide layer which is provided between the first electrode and the second electrode and changes its resistance value in response to a voltage pulse applied between the first electrode and the second electrode,

wherein the metal oxide layer has a first oxide region connected to the first electrode, and a second oxide region connected to the second electrode and having a higher oxygen content atomic percentage than the first oxide region, the method comprising the steps of:

applying a write voltage pulse of a first polarity between the first electrode and the second electrode to change a resistance state of the metal oxide layer from a higher-resistance state to a lower-resistance state to place the metal oxide layer in a write state;

applying an erase voltage pulse of a second polarity which is different from the first polarity between the first electrode and the second electrode to change the resistance state of the metal oxide layer from the lower-resistance state to the higher-resistance state to place the metal oxide layer in an erase state;

before the resistance value of the metal oxide layer first attaining a resistance value RL corresponding to the write state, changing the resistance value of the metal oxide layer from a resistance value R 0 corresponding to an initial state of the metal oxide layer to another resistance value R 2 , by applying at least a first initial voltage pulse of the first polarity between the first electrode and the second electrode; and

before the resistance value of the metal oxide layer first attaining the resistance value RL corresponding to the write state, applying a second initial voltage pulse of the second polarity between the first electrode and the second electrode, to change the resistance value of the metal oxide layer from the another resistance value R 2 to the resistance value RH corresponding to the erase state,

wherein when a maximum value of a current flowing through the metal oxide layer when the first initial voltage pulse is applied is IbRL, and a maximum value of the current flowing through the metal oxide layer when the write voltage pulse is applied is IRL,

R 0 >RH>R 2 >RL, and

|IRL|>|IbRL| are satisfied.

2. The method of driving the variable resistance element according to claim 1 ,

wherein the maximum value IRL of the current flowing through the metal oxide layer when the write voltage pulse is applied satisfies a relationship of |IRL|>|IbRL|×1.18.

3. The method of driving the variable resistance element according to claim 1 ,

wherein the metal oxide layer comprises one of a tantalum oxide, a hafnium oxide, and a zirconium oxide.

4. The method of driving the variable resistance element according to claim 3 ,

wherein the first oxide region contains an oxide having a composition expressed as TaO x (0.8≦x≦1.9), and the second oxide region contains an oxide having a composition expressed as TaO y (2.1≦y≦2.5).

5. The method of driving the variable resistance element according to claim 1 ,

wherein the maximum value of the current flowing through the metal oxide when the write voltage pulse is applied is increased to be greater in a present write step after the write step has been performed in repetition, than in previous write steps.

6. The method of driving the variable resistance element according to claim 5 , further comprising the step of:

verifying the resistance state of the metal oxide layer after the write step and re-performing the write step when it is determined that the write state has not been implemented, as a result of the verification,

wherein the maximum value of the current flowing through the metal oxide when the write voltage pulse is applied is increased to be greater in a present write step after the verifying step has been performed plural times, than in previous write steps.

7. A non-volatile memory device comprising:

a variable resistance element including a first electrode, a second electrode, and a metal oxide layer which is provided between the first electrode and the second electrode and changes its resistance value in response to a voltage pulse applied between the first electrode and the second electrode; and

a voltage pulse application circuit for applying a predetermined voltage pulse to the variable resistance element;

wherein the metal oxide layer has a first oxide region connected to the first electrode, and a second oxide region connected to the second electrode and having a higher oxygen content atomic percentage than the first oxide region;

wherein the voltage pulse application circuit applies a write voltage pulse of a first polarity between the first electrode and the second electrode to change a resistance state of the metal oxide layer from a higher-resistance state to a lower-resistance state to place the metal oxide layer in a write state;

wherein the voltage pulse application circuit applies an erase voltage pulse of a second polarity which is different from the first polarity between the first electrode and the second electrode to change the resistance state of the metal oxide layer from the lower-resistance state to the higher-resistance state to place the metal oxide layer in an erase state;

wherein before the resistance value of the metal oxide layer first attaining a resistance value RL corresponding to the write state, the voltage pulse application circuit changes the resistance value of the metal oxide layer from a resistance value R 0 corresponding to an initial state of the metal oxide layer to another resistance value R 2 , by applying at least a first initial voltage pulse of the first polarity between the first electrode and the second electrode;

wherein before the resistance value of the metal oxide layer first attaining the resistance value RL corresponding to the write state, the voltage pulse application circuit applies a second initial voltage pulse of the second polarity between the first electrode and the second electrode, to change the resistance value of the metal oxide layer from the another resistance value R 2 to the resistance value RH corresponding to the erase state; and

wherein when the resistance value corresponding to the write state is RL, a maximum value of a current flowing through the metal oxide layer when the first initial voltage pulse is applied is IbRL, and a maximum value of the current flowing through the metal oxide layer when the write voltage pulse is applied is IRL,

R 0 >RH>R 2 >RL, and

|IRL|>|IbRL|are satisfied.

8. The non-volatile memory device according to claim 7 ,

wherein the maximum value IRL of the current flowing through the metal oxide layer when the write voltage pulse is applied satisfies a relationship of |IRL|≧|IbRL|×1.18.

9. The non-volatile memory device according to claim 7 ,

wherein the metal oxide layer comprises one of a tantalum oxide, a hafnium oxide, and a zirconium oxide.

10. The non-volatile memory device according to claim 9 ,

wherein the first oxide region contains an oxide having a composition expressed as TaO x (0.8≦x≦1.9); and

wherein the second oxide region contains an oxide having a composition expressed as TaO y (2.1≦y≦2.5).

11. The non-volatile memory device according to claim 7 ,

wherein the voltage pulse application circuit is configured to apply the write voltage pulse such that the current of a magnitude greater than a maximum value of the current flowing through the metal oxide layer when the write voltage pulse has been applied in repetition is flowed, in a case where the voltage pulse application circuit applies the write voltage pulse after the voltage pulse application circuit has applied the write voltage pulse in repetition.

12. The non-volatile memory device according to claim 11 , further comprising:

a verification means which verifies the resistance state of the metal oxide layer after the write voltage pulse is applied;

wherein the voltage pulse application circuit is configured to re-apply the write voltage pulse when the verification means determines that the write state has not been implemented, as a result of the verification; and

wherein the voltage pulse application circuit is configured to apply the write voltage pulse such that the current of a magnitude greater than a maximum value of the current flowing through the metal oxide layer when the write voltage pulse has been re-applied plural times is flowed, in a case where the voltage pulse application circuit applies the write voltage pulse after the voltage pulse application circuit has re-applied the write voltage pulse plural times.

13. The non-volatile memory device according to claim 7 , further comprising:

a current steering element electrically connected to the first electrode or the second electrode.

14. The non-volatile memory device according to claim 13 , wherein the current steering element is a transistor.

15. The non-volatile memory device according to claim 13 , wherein the current steering element is a diode.