IP Library Granted Patent US 9,105,823
Granted Patent B2
US 9,105,823 · App. 13/983,972 · Granted Aug 11, 2015

Optoelectronic semiconductor chip and method for producing an optoelectronic semiconductor chip

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Quick Facts
Patent No.
US 9,105,823
App. No.
13/983,972
Granted
Aug 11, 2015
Kind
B2
Abstract

An optoelectronic semiconductor chip has an epitaxial layer sequence. A doped epitaxial layer of the epitaxial layer sequence has a first region and a second region and a protected structure. The first region of the doped epitaxial layer completely covers the protected structure. The outer surface of the doped epitaxial layer has a first roughness in the first region and a second roughness in the second region.

Claims (34)

1. An optoelectronic semiconductor chip comprising:

an epitaxial layer sequence comprising a doped epitaxial layer comprising a first region and a second region and a protected structure,

wherein the first region of the doped epitaxial layer completely covers the protected structure, and

wherein an outer surface of the doped epitaxial layer has a first roughness in the first region and a second roughness in the second region.

2. The optoelectronic semiconductor chip according to claim 1 , wherein the first roughness is formed by depressions having depths of less than approximately 0.5 μm, voids and surface defects.

3. The optoelectronic semiconductor chip according to claim 2 , wherein the depressions comprise hole-shaped depressions.

4. The optoelectronic semiconductor chip according to claim 1 , wherein the first roughness is formed by pyramidal depressions having etching depths of up to approximately 1 μm.

5. The optoelectronic semiconductor chip according to claim 1 , wherein the second roughness is formed by pyramidal depressions having etching depths of approximately 0.5 μm to approximately 4 μm.

6. The optoelectronic semiconductor chip according to claim 5 , wherein the first roughness is formed by pyramidal depressions having etching depths of up to approximately 1 μm.

7. The optoelectronic semiconductor chip according to claim 1 , wherein at least one of the first roughness and the second roughness is formed by pyramidal depressions having side faces, which form an angle of 35° to 75° with a plane of the epitaxial layer sequence.

8. The optoelectronic semiconductor chip according to claim 7 , wherein the side faces form an angle of 50° to 70° with the plane of the epitaxial layer sequence.

9. The optoelectronic semiconductor chip according to claim 1 , wherein the protected structure comprises at least one contact recess that traverses the epitaxial layer sequence parallel to a growth direction thereof and produces an electrical contact with the doped epitaxial layer.

10. The optoelectronic semiconductor chip according to claim 1 , wherein the protected structure comprises a circumferential edge of the epitaxial layer sequence.

11. The optoelectronic semiconductor chip according to claim 1 , wherein the doped epitaxial layer is n-doped.

12. The optoelectronic semiconductor chip according to claim 1 , wherein the first region is covered by a protective mask.

13. The optoelectronic semiconductor chip according to claim 1 , wherein the optoelectronic semiconductor chip further comprises a protective mask, wherein the protective mask is applied on the outer surface above the protected structure.

14. The optoelectronic semiconductor chip according to claim 1 , wherein the optoelectronic semiconductor chip comprises a multiplicity of first regions, a multiplicity of second regions, and a multiplicity of protected structures, wherein each first region is assigned to a protected structure in a one-to-one manner.

15. The optoelectronic semiconductor chip according to claim 14 , wherein each first region is laterally enclosed by second regions.

16. A method for producing an optoelectronic semiconductor chip, the method comprising:

providing an epitaxial layer sequence comprising a doped epitaxial layer having an outer surface;

applying a structured protective mask to the outer surface; and

etching the doped epitaxial layer, wherein the protective mask is applied on the outer surface above the at least one contact recess, wherein a first region having a first roughness remains on the outer surface covered by the protective mask, and wherein a second region having a second roughness is produced on that region of the outer surface which is not covered by the protective mask.

17. The method according to claim 16 , wherein the protective mask is applied on the outer surface above a circumferential edge of the epitaxial layer sequence.

18. The method according to claim 16 , further comprising removing the protective mask after the doped epitaxial layer has been etched.

19. The method according to claim 18 , further comprising etching the first region of the doped epitaxial layer after the protective mask has been removed.

20. The method according to claim 16 , wherein the protective mask remains on the doped epitaxial layer after etching.

21. An optoelectronic semiconductor chip comprising:

an epitaxial layer sequence comprising a doped epitaxial layer comprising a first region and a second region and a protected structure,

wherein the first region of the doped epitaxial layer completely covers the protected structure,

wherein an outer surface of the doped epitaxial layer has a first roughness in the first region and a second roughness in the second region,

wherein the doped epitaxial layer has a first average thickness in the first region,

wherein second roughness of the second region is formed by depressions in the epitaxial layer, and

wherein at least one depression has a step height parallel to a growth direction greater than the first average thickness.

22. The optoelectronic semiconductor chip according to claim 21 , wherein at least one depression of the second region in a direction parallel to the growth direction extends as far as the protected structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2020
From: OSRAM OPTO SEMICONDUCTORS GMBH
To: OSRAM OLED GMBH
Reel/Frame 051467/0906 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2013
From: ENGL, KARL; EIBL, JOHANN; LAMFALUSI, TAMAS; MAUTE, MARKUS
To: OSRAM OPTO SEMICONDUCTORS GMBH
Reel/Frame 031397/0456 →