Electronic devices

1. A device comprising an array of transistors, including:

patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and pairs of source and drain electrodes of the array of transistors, and drain pads each connected to a respective drain electrode and providing the base of a respective interlayer conductive link to a higher level; and

a semiconductor layer providing semiconductor channels between the source and drain electrodes of the source-drain electrode pairs;

wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and

wherein said drain pads overlap with said further patterned conductive layer via said dielectric layer without overlapping of said semiconductor channels with said further patterned conductive layer; and

wherein said further patterned conductive layer defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.

2. A device according to claim 1 , wherein the device substrate comprises an organic upper surface.

3. A device according to claim 2 , wherein the device substrate comprises an organic polymer support coated with an organic planarising layer.

4. A device according to claim 1 , wherein the dielectric layer comprises an inorganic material.

5. A device according to claim 1 , wherein the semiconductor layer comprises an organic material, and the stack further includes a layer of organic material to provide gate dielectric elements between the semiconductor channels and overlying gate conductors.

6. A device according to claim 1 , wherein the dielectric layer has a dielectric constant of greater than about 5.

7. A device according to claim 6 , wherein the dielectric layer has a dielectric constant between about 5 and about 9.3.

8. A device comprising an array of transistors, including:

a first patterned conductive layer defining source-drain electrodes of the array of transistors; and

patterned upper and lower conductive layers above and below the first patterned conductive layer;

wherein the patterned upper and lower conductive layers both define gate lines for the array of transistors;

wherein the array of transistors includes a mixed array of bottom-gate transistors and top-gate transistors; the lower patterned conductive layer defines a set of bottom gate lines; and the upper patterned conductive layer defines a set of top gate lines, each top gate line located between a respective pair of the bottom gate lines.

9. A device according to claim 8 , wherein both the bottom-gate transistors and the top-gate transistors include drain pads, each drain pad providing a base for an interlayer conductive connection to a respective pixel electrode at a higher level.

10. A device according to claim 9 , wherein the top gate lines comprise one or more gate lines that overlap one or more of said drain pads; and said one or more of said drain pads overlap one or more of said bottom-gate lines.

11. A device according to claim 8 , wherein each top-gate line provides gate electrodes for a respective group of said top-gate transistors, and each bottom-gate line provides gate electrodes for a respective group of said bottom-gate transistors.

12. A device according to claim 8 , wherein each top gate line is associated with a respective group of said top-gate transistors, each one of said group of top-gate transistors being addressable by the same top-gate line; and wherein each bottom gate line is associated with a respective group of said bottom-gate transistors, each one of said group of bottom-gate transistors being addressable by the same bottom gate line.