IP Library Granted Patent US 8,981,333
Granted Patent B2
US 8,981,333 · App. 13/991,964 · Granted Mar 17, 2015

Nonvolatile semiconductor memory device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,981,333
App. No.
13/991,964
Granted
Mar 17, 2015
Kind
B2
Abstract

Provided is a nonvolatile semiconductor memory device including a variable resistance element in which a parasitic resistance between the lower electrode and the variable resistance layer included in the variable resistance element is reduced. The nonvolatile semiconductor memory device includes: a substrate; and a variable resistance elementformed on the substrate, wherein the variable resistance elementincludes a lower electrode layer formed on the substrate, a variable resistance layer formed on the lower electrode layer, and an upper electrode layer formed on the variable resistance layer, the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer, and the first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer.

Claims (42)

1. A variable resistance nonvolatile semiconductor memory device comprising:

a substrate; and

a variable resistance element formed on the substrate, having a resistance value which changes in response to application of an electric pulse, and holding the changed resistance value,

wherein the variable resistance element includes (i) a lower electrode layer formed on the substrate, (ii) a variable resistance layer formed on the lower electrode layer and comprising a metal oxide, and (iii) an upper electrode layer formed on the variable resistance layer,

the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer, and

the first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer.

2. The nonvolatile semiconductor memory device according to claim 1 ,

wherein an oxygen content in vicinity of an interface between the variable resistance layer and the second conductive layer is smaller than an oxygen content in vicinity of an interface between the second conductive layer and the first conductive layer.

3. The nonvolatile semiconductor memory device according to claim 1 ,

wherein the second conductive layer and the variable resistance layer are continuously formed without being exposed to an atmosphere.

4. The nonvolatile semiconductor memory device according to claim 1 , further comprising

a non-ohmic element formed on the upper electrode layer,

wherein the non-ohmic element includes (i) a first electrode layer formed on the upper electrode layer, (ii) a semiconductor layer or an insulating layer formed on the first electrode layer, and (iii) a second electrode layer formed on the semiconductor layer or the insulating layer.

5. The nonvolatile semiconductor memory device according claim 1 ,

wherein the variable resistance layer is an oxygen-deficient metal oxide.

6. The nonvolatile semiconductor memory device according to claim 5 ,

wherein the variable resistance layer includes a first variable resistance layer and a second variable resistance layer which are metal oxides having a different degree of oxygen deficiency.

7. A method of manufacturing a variable resistance nonvolatile semiconductor memory device, the method comprising

forming, on a substrate, a variable resistance element having a resistance value which changes in response to application of an electric pulse, and holding the changed resistance value,

wherein the forming includes:

forming a lower electrode layer on the substrate;

forming, on the lower electrode layer, a variable resistance layer comprising a metal oxide; and

forming an upper electrode layer on the variable resistance layer,

the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer,

the first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer, and

the second conductive layer and the variable resistance layer are continuously formed without being exposed to an atmosphere.

8. The method according to claim 7 ,

wherein the forming of a lower electrode layer includes:

forming, on the substrate, a lower electrode material layer which is for forming the first conductive layer;

forming the first conductive layer which includes, on its upper surface, the oxidatively degraded layer by performing chemical mechanical polishing on the lower electrode material layer; and

forming the second conductive layer on the first conductive layer.

9. The method according to claim 8 , further comprising:

forming lower electrode lines in a stripe pattern on the substrate;

forming an interlayer insulating layer on the substrate including surfaces of the lower electrode lines;

forming, in the interlayer insulating layer, contact holes at positions facing the lower electrode lines;

forming, on the upper electrode layer, a first electrode layer which is to be a part of a non-ohmic element;

forming, on the first electrode layer, a semiconductor layer or an insulating layer which is to be a part of the non-ohmic element; and

forming, on the semiconductor layer or the insulating layer, second electrode layers each of which is to be a part of the non-ohmic element, the second electrode layers being in a stripe pattern and three-dimensionally crossing the lower electrode lines,

wherein in the forming of a lower electrode material layer, the lower electrode material layer is formed on the contact holes and the interlayer insulating layer, and

in the performing of chemical mechanical polishing, the lower electrode material layer on the interlayer insulating layer is removed.

10. The method according to claim 7 ,

wherein the forming of a variable resistance element further includes removing the oxidatively degraded layer between forming the first conductive layer and forming the second conductive layer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2014
From: FUJII, SATORU; ITO, SATORU; MIKAWA, TAKUMI
To: PANASONIC CORPORATION
Reel/Frame 032125/0454 →