Source/drain contacts for non-planar transistors
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
1. A microelectronic device, comprising:
a non-planar transistor gate over a non-planar transistor fin, wherein the non-planar transistor gate comprises a gate electrode recessed between gate spacers and a capping structure disposed on the recessed gate electrode between the gate spacers,
a silicon-containing source/drain region;
at least one dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping structure;
a source/drain contact extending through a portion of the at least one dielectric material layer and comprising a conductive contact material and a titanium-containing contact interface layer disposed between conductive contact material and the silicon-containing source/drain region; and
a titanium silicide interface disposed between the silicon-containing source/drain region and the titanium-containing contact interface layer.
2. The microelectronic device of claim 1 , wherein the titanium-containing contact interface layer comprises substantially pure titanium.
3. The microelectronic device of claim 1 , wherein the conductive contact material comprises tungsten.
4. The microelectronic device of claim 1 , wherein the titanium silicide interface resides substantially only between the silicon-containing source/drain region and the titanium-containing contact interface layer.
5. The microelectronic device of claim 1 , wherein the titanium-containing contact interface layer abuts at least a portion of one non-planar transistor gate spacer.
6. The microelectronic device of claim 5 , wherein the titanium-containing contact interface layer abuts at least a portion of the capping structure.
7. A method comprising:
forming a sacrificial non-planar transistor gate over a non-planar transistor fin;
depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin;
forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;
forming a source/drain region;
removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;
forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;
depositing conductive gate material within the gate trench forming a capping structure within the recess;
forming at least one dielectric material over the source/drain region, the non-planar transistor gate spacers, and the capping structure;
forming a contact opening through the at least one dielectric material to expose at least a portion of the source/drain region;
conformally depositing a titanium-containing contact interface layer within the contact opening to abut the silicon-containing source/drain region;
depositing a conductive contact material within the contact opening to abut the titanium-containing contact interface layer; and
forming a titanium silicide interface between the silicon-containing source/drain region and the titanium-containing contact interface layer.
8. The method of claim 7 , wherein conformally depositing the titanium-containing contact interface layer comprises conformally depositing a substantially pure titanium contact interface layer.
9. The method of claim 7 , wherein depositing a conductive contact material within the contact opening comprises depositing tungsten within the contact opening.
10. The method of claim 7 , wherein forming the titanium silicide interface between the silicon-containing source/drain region and the titanium-containing contact interface layer comprises forming the titanium silicide interface between the silicon-containing source/drain region and the titanium-containing contact interface layer by heating the silicon-containing source/drain region and the titanium-containing contact interface layer.
11. The method of claim 7 , wherein forming the titanium silicide interface comprises forming the titanium silicide substantially only between the silicon-containing source/drain region and the titanium-containing contact interface layer.
12. The method of claim 7 , wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material to expose a portion of the source/drain region and at least a portion of one non-planar transistor gate spacer.
13. The method of claim 12 , wherein the forming the titanium-containing contact interface layer further comprises forming the titanium-containing contact interface layer to abut at least a portion of one non-planar transistor gate spacer.
14. The method of claim 7 , wherein forming a contact opening through the dielectric material to expose at least a portion of the source/drain region further comprises forming a contact opening through the dielectric material to expose a portion of the source/drain region and at least a portion of the capping structure.
15. The method of claim 14 , wherein the forming the titanium-containing contact interface layer further comprises forming the titanium-containing contact interface layer to abut at least a portion of the capping structure.