IP Library › Patent Application 13996108

Patent Application

App. No. 13/996,108

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

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App. No.: 13/996,108

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Abstract

A data processing device and a data processing method capable of improving resistance to error of data. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 4/15, 7/15, or 8/15. A parity check matrix of the LDPC code is composed by arrangement of an element of an information matrix determined by a parity check matrix initial value table indicating a position of the element of the information matrix corresponding to an information length corresponding to the code length and the code rate for each 360 columns of the parity check matrix with a period of 360 columns in a column direction. The parity check matrix initial value table is for digital broadcasting for a mobile terminal, for example. This technology may be applied to a case in which LDPC encoding and LDPC decoding are performed.

Claims (313)

1 . A data processing device, comprising:

an encoder, which encodes information bits into a cord word whose code length is 16200 bits and code rate is 4/15 based on a parity check matrix of an LDPC (low density parity check) code, wherein

the LDPC code encoded by the encoder includes an information bit and a parity bit,

the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,

the information matrix part is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table indicating a position of an element 1 of the information matrix part for each 360 columns as

1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699

514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598

483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879

1956 7572 9020 9971

13 1578 7445 8373

6805 6857 8615 11179

7983 8022 10017 11748

4939 8861 10444 11661

2278 3733 6265 10009

4494 7974 10649

8909 11030 11696

3131 9964 10480.

2 . A data processing device, comprising:

an encoder, which encodes information bits into a cord word whose code length is 16200 bits and code rate is 7/15 based on a parity check matrix of an LDPC (low density parity check) code, wherein

the LDPC code encoded by the encoder includes an information bit and a parity bit,

the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,

the information matrix part is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table indicating a position of an element 1 of the information matrix part for each 360 columns as

3 137 314 327 983 1597 2028 3043 3217 4109 6020 6178 6535 6560 7146 7180 7408 7790 7893 8123 8313 8526 8616 8638

356 1197 1208 1839 1903 2712 3088 3537 4091 4301 4919 5068 6025 6195 6324 6378 6686 6829 7558 7745 8042 8382 8587 8602

18 187 1115 1417 1463 2300 2328 3502 3805 4677 4827 5551 5968 6394 6412 6753 7169 7524 7695 7976 8069 8118 8522 8582

714 2713 2726 2964 3055 3220 3334 3459 5557 5765 5841 6290 6419 6573 6856 7786 7937 8156 8286 8327 8384 8448 8539 8559

3452 7935 8092 8623

56 1955 3000 8242

1809 4094 7991 8489

2220 6455 7849 8548

1006 2576 3247 6976

2177 6048 7795 8295

1413 2595 7446 8594

2101 3714 7541 8531

10 5961 7484

3144 4636 5282

5708 5875 8390

3322 5223 7975

197 4653 8283

598 5393 8624

906 7249 7542

1223 2148 8195

976 2001 5005.

3 . A data processing device, comprising:

an encoder, which encodes information bits into a cord word whose code length is 16200 bits and code rate is 8/15 based on a parity check matrix of an LDPC (low density parity check) code, wherein

the LDPC code encoded by the encoder includes an information bit and a parity bit,

the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,

the information matrix part is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table indicating a position of an element 1 of the information matrix part for each 360 columns as

32 384 430 591 1296 1976 1999 2137 2175 3638 4214 4304 4486 4662 4999 5174 5700 6969 7115 7138 7189

1788 1881 1910 2724 4504 4928 4973 5616 5686 5718 5846 6523 6893 6994 7074 7100 7277 7399 7476 7480 7537

2791 2824 2927 4196 4298 4800 4948 5361 5401 5688 5818 5862 5969 6029 6244 6645 6962 7203 7302 7454 7534

574 1461 1826 2056 2069 2387 2794 3349 3366 4951 5826 5834 5903 6640 6762 6786 6859 7043 7418 7431 7554

14 178 675 823 890 930 1209 1311 2898 4339 4600 5203 6485 6549 6970 7208 7218 7298 7454 7457 7462

4075 4188 7313 7553

5145 6018 7148 7507

3198 4858 6983 7033

3170 5126 5625 6901

2839 6093 7071 7450

11 3735 5413

2497 5400 7238

2067 5172 5714

1889 7173 7329

1795 2773 3499

2695 2944 6735

3221 4625 5897

1690 6122 6816

5013 6839 7358

1601 6849 7415

2180 7389 7543

2121 6838 7054

1948 3109 5046

272 1015 7464.

4 . The data processing device according to claim 1 , further comprising:

a parity interleaver, which interleaves only the parity bit of the LDPC code.

5 . The data processing device according to claim 1 , further comprising:

a column twist interleaver, which performs column twist interleave by recording a code bit of the LDPC code while shifting in a column direction.

6 . The data processing device according to claim 1 , wherein

a 2+360×(i−1)-th column of the parity check matrix is a column obtained by cyclic shift of a 1+360×(i−1)-th column indicated by the parity check matrix initial value table downward by q=M/360 (i represents the number of rows of the parity check matrix initial table and M represents a parity length).

7 . The data processing device according to claim 6 , wherein

q is set to 33.

8 . The data processing device according to claim 1 , wherein

as for a 1+360×(i−1)-th column of the parity check matrix,

an i-th row of the parity check matrix initial value table indicates a row number of an element 1 of the 1+360×(i−1)-th column of the parity check matrix,

as for each column from a 2+360×(i−1)-th column to a 360×i-th column other than the 1+360×(i−1)-th column of the parity check matrix,

when an i-th row j-th column value of the parity check matrix initial value table, the row number of a j-th element 1 of a w-th column of the parity check matrix H, and a parity length are represented as h i,j , H w-j , and M, respectively, the row number H w-j of the element 1 of the w-th column other than the 1+360×(i−1)-th column of the parity check matrix is represented by an equation H w-j =mod {h i,j +mod((w−1), 360)×M/360, M).

9 . A data processing method, comprising:

an encoding step of encoding information bits into a cord word whose code length is 16200 bits and code rate is 4/15 based on a parity check matrix of an LDPC (low density parity check) code, wherein

the LDPC code encoded by the encoding step includes an information bit and a parity bit,

the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,

the information matrix part is represented by a parity check matrix initial value table, and

the parity check matrix initial value table is a table indicating a position of an element 1 of the information matrix part for each 360 columns as

1953 2331 2545 2623 4653 5012 5700 6458 6875 7605 7694 7881 8416 8758 9181 9555 9578 9932 10068 11479 11699

514 784 2059 2129 2386 2454 3396 5184 6624 6825 7533 7861 9116 9473 9601 10432 11011 11159 11378 11528 11598

483 1303 1735 2291 3302 3648 4222 4522 5511 6626 6804 7404 7752 7982 8108 8930 9151 9793 9876 10786 11879

1956 7572 9020 9971

13 1578 7445 8373

6805 6857 8615 11179

7983 8022 10017 11748

4939 8861 10444 11661

2278 3733 6265 10009

4494 7974 10649

8909 11030 11696

3131 9964 10480.

10 . A data processing method, comprising:

an encoding step of encoding information bits into a cord word whose code length is 16200 bits and code rate is 7/15 based on a parity check matrix of an LDPC (low density parity check) code, wherein