IP Library Granted Patent US 9,122,286
Granted Patent B2
US 9,122,286 · App. 13/996,160 · Granted Sep 1, 2015

Integrated circuit apparatus, three-dimensional integrated circuit, three-dimensional processor device, and process scheduler, with configuration taking account of heat

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Quick Facts
Patent No.
US 9,122,286
App. No.
13/996,160
Granted
Sep 1, 2015
Kind
B2
Abstract

The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit. The first circuit is partitioned into a plurality of circuit blocks according to the distance from the arranged position of the second circuit, and the control circuit controls the partitioned respective circuit blocks separately.

Claims (16)

1. An integrated circuit apparatus, comprising:

a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit,

wherein the first circuit is partitioned into a plurality of circuit blocks according to the direction of conduction by the heat generated as a result of operation of the second circuit,

wherein the control circuit controls the partitioned respective circuit blocks separately, and

wherein the control circuit controls each of said plurality of circuit blocks independently for the first circuit not to exceed an operable temperature range under influence of heat generated as a result of operation of the second circuit.

2. The integrated circuit apparatus according to claim 1 , wherein

the control circuit controls supply, cutoff and/or change of power voltage for the partitioned respective circuit blocks separately.

3. The integrated circuit apparatus according to claim 2 , wherein

the control circuit controls each of said plurality of circuit blocks independently, based on a temperature inside each circuit block, a time period measured by a timer included in each circuit block, a frequency of a clock signal supplied to said second circuit, and/or a rate of operation of the arithmetic circuit in said second circuit.

4. The integrated circuit apparatus according to claim 1 , wherein

said integrated circuit apparatus is a three-dimensional integrated circuit which is made of more than two chips stacked, and further comprises a heat sink, and

the control circuit is arranged in the chip at the stacked position nearest to said heat sink.

5. The integrated circuit apparatus according to claim 1 , wherein

the memory circuit is made of cache memory,

the cache memory in the same layer is partitioned to the plurality of circuit blocks, and

the arithmetic circuit is a processor core.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2014
From: MORIMOTO, TAKASHI; KAI, KOUJI
To: PANASONIC CORPORATION
Reel/Frame 032115/0202 →