Dynamic window to improve NAND endurance
View Patent ↗Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
1. An apparatus comprising:
memory controller logic to apply a first trim profile to a flash memory storage device; and
the first trim profile to dynamically cause a program-erase window to vary by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the flash memory storage device based on a current cycle count value,
wherein the memory controller logic is to apply a second trim profile to the flash memory storage device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition, wherein a smaller program-erase window is to be utilized during an initial life of the flash memory.
2. The apparatus of claim 1 , wherein the occurrence of the failure condition is to be detected based on a ECC (Error Correcting Code) event.
3. The apparatus of claim 1 , wherein the occurrence of the failure condition is to be detected based on a Block Fail Rate (BFR) value.
4. The apparatus of claim 1 , further comprising a storage device or register to store the current cycle count value.
5. The apparatus of claim 1 , wherein the flash memory storage device comprises a NAND storage device.
6. The apparatus of claim 1 , wherein the program-erase window corresponds to a Multi Level Cell (MLC) window.
7. The apparatus of claim 1 , wherein one or more processor cores are coupled to the memory controller logic to access data stored in the flash memory storage device.
8. An apparatus comprising:
memory controller logic to apply a first trim profile to a flash memory storage device; and
the first trim profile to dynamically cause a program-erase window to vary by starting with a higher program verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the flash memory storage device based on a current cycle count value,
wherein the memory controller logic is to apply a second trim profile to the flash memory storage device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition, wherein a smaller program-erase window is to be utilized during an initial life of the flash memory.
9. The apparatus of claim 8 , wherein a delta between the PV and TEV voltages is to be kept fixed.
10. The apparatus of claim 8 , wherein the occurrence of the failure condition is to be detected based on a ECC (Error Correcting Code) event.
11. The apparatus of claim 8 , wherein the occurrence of the failure condition is to be detected based on a Block Fail Rate (BFR) value.
12. The apparatus of claim 8 , further comprising a storage device or register to store the current cycle count value.
13. The apparatus of claim 8 , wherein the flash memory storage device comprises a NAND storage device.
14. The apparatus of claim 8 , wherein the program-erase window corresponds to a Multi Level Cell (MLC) window.
15. The apparatus of claim 8 , wherein one or more processor cores are coupled to the memory controller logic to access data stored in the flash memory storage device.
16. A system comprising:
a NAND memory device having a plurality of memory cells;
a processor to access the NAND memory device; and
NAND memory controller logic to apply a first trim profile to the NAND memory device, the first trim profile to:
dynamically cause a program-erase window to vary by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value; or
dynamically cause a program-erase window to vary by starting with a higher program verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value,
wherein the NAND memory controller logic is to apply a second trim profile to the NAND memory device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition, wherein a smaller program-erase window is to be utilized during an initial life of the flash memory.
17. The system of claim 16 , wherein the occurrence of the failure condition is to be detected based on a ECC (Error Correcting Code) event.
18. The system of claim 16 , wherein the occurrence of the failure condition is to be detected based on a Block Fail Rate (BFR) value.
19. The system of claim 16 , further comprising a storage device or register to store the current cycle count value.
20. The system of claim 16 , wherein the program-erase window corresponds to a Multi Level Cell (MLC) window.
21. The system of claim 16 , further comprising an audio device.
22. The system of claim 16 , wherein one or more of the processor, NAND memory device, and the NAND controller logic are on a same integrated circuit die.
23. A method comprising:
applying a first trim profile to a flash memory storage device by memory controller logic, wherein the first trim profile:
dynamically causes a program-erase window to vary by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the flash memory storage device based on a current cycle count value; or
dynamically causes a program-erase window to vary by starting with a higher program verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the flash memory storage device based on the current cycle count value; and
applying a second trim profile to the flash memory storage device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition, wherein a smaller program-erase window is utilized during an initial life of the flash memory.
24. The method of claim 23 , further comprising detecting the occurrence of the failure condition based on occurrence of a ECC (Error Correcting Code) event.
25. The method of claim 23 , further comprising detecting the occurrence of the failure condition based on a Block Fail Rate (BFR) value.