Parallel memory systems
The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
1. A multi-core processor memory system, comprising:
a main memory including a plurality of memory blocks;
a plurality of memory controllers coupled to the plurality of memory blocks;
a plurality of memory channels provided between a multi-core general-purpose processor and the main memory, the multi-core processor including a plurality of processor cores;
the plurality of memory channels comprising at least as many memory channels as processor cores,
each memory channel being associated with one of the processor cores,
the plurality of memory channels operative to selectively connect each of the plurality of processor cores to each of the plurality of memory blocks, and
the multi-core processor memory system configured to dynamically relate at run-time one or more of the memory blocks dedicatedly to an accessing processor core of the plurality of processor cores,
the accessing processor core having dedicated access to the one or more memory blocks via the associated memory channel of the accessing processor core; and
at least one switch provided between the plurality of processor cores and the plurality of memory controllers, the at least one switch operative to perform the selective connection of each of the plurality of processor cores to each of the plurality of memory blocks.
2. The system according to claim 1 , wherein the memory channels transmit serial data.
3. The system according to claim 1 , wherein at least one of the memory channels is temporarily exclusive for transmitting data solely between one of the memory blocks and one of the processor cores.
4. The system according to claim 1 , wherein data is transmitted between multiple of the processor cores and multiple of the memory blocks in parallel.
5. The system according to claim 4 , wherein each of the transmissions of data is independent of the other transmissions of data between the multiple processor cores and the multiple memory blocks.
6. The system according to claim 4 , wherein the transmissions of data do not impair the other transmissions of data between the multiple processor cores and the multiple memory blocks.
7. The system according to claim 1 , wherein each of the plurality of memory channels is connected to an associated dedicated memory controller of the plurality of memory controllers.
8. The system according to claim 1 , further comprising at least one level-1 cache provided between at least one of the plurality of processor cores and the at least one switch.
9. The system according to claim 8 , further comprising at least one level-2 cache provided between at least one of the plurality of processor cores and the at least one switch.
10. The system according to claim 1 , wherein the plurality of memory channels includes:
a plurality of first connections between the plurality of processor cores and the at least one switch; and
a plurality of second connections between the at least one switch and the plurality of memory blocks.
11. The system of claim 10 wherein the plurality of first connections are at least as numerous as the plurality of second connections.
12. The system of claim 10 wherein the plurality of second connections are at least as numerous as the plurality of processor cores.
13. The system according to claim 10 , wherein each of the plurality of second connections corresponds to a different one of the plurality of first connections.
14. The system according to claim 1 , wherein for at least one processor core of the plurality of processor cores, a particular processor core is connected to multiple memory channels of the plurality of memory channels, wherein the multiple memory channels connect the particular processor core to the at least one switch.
15. The system according to claim 1 , wherein the plurality of memory channels include a separate connection to each the plurality of memory blocks, wherein a number of the separate connections is at least a number of the plurality of processor cores.
16. The system according to claim 1 , wherein each of the processor cores comprises a plurality of load/store units, each load/store unit configured to supply information to one memory channel of the plurality of memory channels.
17. The system according to claim 1 , wherein each of the plurality of memory controllers is directly connected to an associated memory block of the plurality of memory blocks.
18. The system according to claim 1 , wherein the plurality of memory channels are arranged in parallel and configured to communicate data to and from the plurality of memory blocks in parallel.
19. The system according to claim 18 , wherein the plurality of memory channels are configurably connectable to the plurality of memory blocks to configure which of the plurality of memory channels are connected to respective memory blocks of the plurality of memory blocks.