IP Library Granted Patent US 9,209,309
Granted Patent B2
US 9,209,309 · App. 14/003,946 · Granted Dec 8, 2015

Method for fabricating thin-film semiconductor device and thin-film semiconductor device

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Quick Facts
Patent No.
US 9,209,309
App. No.
14/003,946
Granted
Dec 8, 2015
Kind
B2
Abstract

A thin-film semiconductor device) having two thin-film transistors, wherein one of the thin-film transistors includes: a first gate electrode; a first gate insulating film; a first semiconductor film; an intrinsic semiconductor layer; a first contact layer of n-type in contact with and above a portion of the intrinsic semiconductor layer; a first source electrode; and a first drain electrode, and the other of the thin-film transistors includes: a second gate electrode; a second gate insulating film; a second semiconductor film; an intrinsic semiconductor layer; a second contact layer of p-type in contact with portions of sides of the semiconductor film and the intrinsic semiconductor layer; a second source electrode; and a second drain electrode.

Claims (43)

1. A thin-film semiconductor device having at least a first thin-film transistor and a second thin-film transistor,

wherein the first thin-film transistor includes:

a first gate electrode;

a first insulating film on the first gate electrode;

a first semiconductor layer which is on the first insulating film and has, as a channel region, a region that is opposite to the first gate electrode with the first insulating film therebetween;

a first contact layer of a first conductivity type in contact with and above at least a portion of the semiconductor layer;

a first source electrode on the first contact layer; and

a first drain electrode opposite to the first source electrode on the first contact layer, and

the second thin-film transistor includes:

a second gate electrode;

a second insulating film on the second gate electrode;

a second semiconductor layer which is on the second insulating film and has, as a channel region, a region that is opposite to the second gate electrode with the second insulating film therebetween;

a second contact layer of a second conductivity type in contact with at least a portion of sides of the semiconductor layer, the second conductivity type being different from the first conductivity type;

a second source electrode on the second contact layer; and

a second drain electrode opposite to the second source electrode on the second contact layer.

2. The thin-film semiconductor device according to claim 1 ,

wherein the first contact layer and the second contact layer have an average grain size smaller than an average grain size of the channel regions.

3. The thin-film semiconductor device according to claim 1 ,

wherein the first thin-film transistor has a first channel protection layer above the first semiconductor layer, and

in the first thin-film transistor, the first channel protection layer has a channel direction length less than a channel direction length of the first semiconductor layer.

4. The thin-film semiconductor device according to claim 1 ,

wherein the second thin-film transistor has a second channel protection layer above the second semiconductor layer, and

in the second thin-film transistor, the second channel protection layer has a channel direction length equal to a channel direction length of the second semiconductor layer.

5. The thin-film semiconductor device according to claim 1 ,

wherein each of the first semiconductor layer and the second semiconductor layer includes a semiconductor film and an intrinsic semiconductor layer that is non-crystalline and formed above the semiconductor film, and

the first conductivity type is an n-type, and the second conductivity type is a p-type.

6. The thin-film semiconductor device according to claim 1 ,

wherein each of the first contact layer and the second contact layer is formed above a corresponding one of the first channel protection layer and the second channel protection layer.

7. The thin-film semiconductor device according to claim 1 ,

wherein the first insulating film and the second insulating film are connected.

8. The thin-film semiconductor device according to claim 1 ,

wherein at least one of the first semiconductor layer and the second semiconductor layer includes:

a semiconductor film; and

an intrinsic semiconductor layer that is non-crystalline and formed between the semiconductor film and a channel protection layer.

9. The thin-film semiconductor device according to claim 8 ,

wherein E cp <E c1 is satisfied, where energy levels at lower edges of conduction bands of the semiconductor film and the intrinsic semiconductor layer are E cp and E c1 , respectively.

10. The thin-film semiconductor device according to claim 8 ,

wherein the intrinsic semiconductor layer includes a first intrinsic semiconductor film formed on the semiconductor film, and a second intrinsic semiconductor film formed on the first intrinsic semiconductor film, and

the first intrinsic semiconductor film and the second intrinsic semiconductor film have different electron affinities.

11. The thin-film semiconductor device according to claim 10 ,

wherein the first intrinsic semiconductor film has a crystallization rate higher than a crystallization rate of the second intrinsic semiconductor film.

12. The thin-film semiconductor device according to claim 10 ,

wherein an energy level E cp at a lower edge of a conduction band of the semiconductor film and an energy level E c1 at a lower edge of a conduction band of the first intrinsic semiconductor film are adjusted to prevent a spike from occurring in a connection part of the semiconductor film and the first intrinsic semiconductor film.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035187/0483 →
CORRECTIVE ASSIGNMENT TO CORRECT THE WRONG EXECUTION DATE 08/20/2013 OF KENICHIROU NISHIDA PREVIOUSLY RECORDED ON REEL 032198 FRAME 0336. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT EXECUTION DATE IS 08/26/2013. Recorded Feb 19, 2014
From: KANEGAE, ARINOBU; NISHIDA, KENICHIROU
To: PANASONIC CORPORATION
Reel/Frame 032287/0231 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2014
From: KANEGAE, ARINOBU; NISHIDA, KENICHIROU
To: PANASONIC CORPORATION
Reel/Frame 032198/0336 →