Device and method for implementing address buffer management of processor
View Patent ↗The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.
1. A device for implementing address buffer management of a processor, comprising:
an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values, wherein the intermediate values are values for an address automatic-increment operation or an address automatic-decrement operation; and
a processor configured to decode the set instruction to obtain the intermediate values, and to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to achieve the address buffer management.
2. The device according to claim 1 , wherein the assembler comprises:
an instruction encoding unit configured, when the set instruction for the address automatic-increment value and boundary values received by the assembler is set aa,<aa_inc>[aa_start,aa_end], to perform operations according to an automatic-increment value or an automatic-decrement value aa_inc of an address register, a trailing boundary value aa_end and a leading boundary value aa_start of the address buffer so as to obtain a first intermediate value aa_wrap and a second intermediate value aa_test, and
an instruction encapsulating unit configured to encapsulate the set instruction for the address automatic-increment value and boundary values including the aa_inc, the aa_wrap, and the aa_test as a binary instruction machine code.
3. The device according to claim 2 , wherein the processor comprises:
an instruction decoding unit configured to decode the set instruction for the address automatic-increment value and boundary values so as to obtain the aa_inc, the aa_wrap, and the aa_test from the instruction machine code; and
an automatic-increment or automatic-decrement operation unit configured, when performing the load or store instruction, to determine, according to the aa_inc, the aa_wrap and the aa_test, whether to perform the address automatic-increment operation or the address automatic-decrement operation so as to achieve the address buffer management.
4. The device according to claim 3 , wherein the instruction encoding unit is further configured, in the case of aa_inc>0 where the aa_inc is the automatic-increment value of an address increment register,
to perform the following operations to obtain the first intermediate value aa_wrap and the second intermediate value aa_test: aa_wrap=aa_inc−(aa_end−aa_start+1); aa_test=aa_inc−aa_end−1, or
wherein the instruction encoding unit is further configured, in the case of aa_inc<0 where the aa_inc is the automatic-decrement value of the address increment register,
to perform the following operations to obtain the first intermediate value aa_wrap and the second intermediate value aa_test: aa_wrap=aa_inc+(aa_end−aa_start+1); aa_test=aa_inc−aa_start.
5. The device according to claim 3 , wherein the automatic-increment or automatic-decrement operation unit is further configured, after obtaining the aa_wrap and the aa_test, to determine whether a sign bit of the aa_inc is equal to a sign bit of the aa+aa_test so as to achieve the address buffer management, wherein in the case they are equal, aa=aa+aa_wrap, otherwise aa=aa+aa_inc, in which the aa is a current value of the address register.
6. A method for implementing address buffer management of a processor, comprising:
by an assembler, performing operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values;
by the assembler, encapsulating the intermediate values into the set instruction for the address automatic-increment value and boundary values, wherein the intermediate values are values for an address automatic-increment operation or an address automatic-decrement operation;
by a processor, decoding the set instruction to obtain the intermediate values; and
by the processor, determining, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to achieve the address buffer management.
7. The method according to claim 6 , wherein the performing operations to obtain the intermediate values comprises:
in the case that the set instruction for the address automatic-increment value and boundary values received by the assembler is set aa,<aa_inc>[aa_start,aa_end],
performing operations according to an automatic-increment value or an automatic-decrement value aa_inc of an address register, a trailing boundary value aa_end and a leading boundary value aa_start of the address buffer so as to obtain a first intermediate value aa_wrap and a second intermediate value aa_test.
8. The method according to claim 7 , wherein
in the case of aa_inc>0 where the aa_inc is the automatic-increment value of an address increment register,
the first intermediate value aa_wrap and the second intermediate value aa_test are obtained from the following operations: aa_wrap=aa_inc−(aa_end−aa_start+1); aa_test=aa_inc−aa_end−1, or
in the case of aa_inc<0 where the aa_inc is the automatic-decrement value of the address increment register,
the first intermediate value aa_wrap and the second intermediate value aa_test are obtained from the following operations: aa_wrap=aa_inc+(aa_end−aa_start+1); aa_test=aa_inc−aa_start.
9. The method according to claim 8 , wherein determining, according to aa_inc, aa_wrap and aa_test, whether to perform the address automatic-increment operation or the address automatic-decrement operation so as to achieve the address buffer management, comprises:
after obtaining the aa_wrap and the aa_test, determining whether a sign bit of the aa_inc is equal to a sign bit of the aa+aa_test so as to achieve the address buffer management,
wherein in the case they are equal, aa=aa+aa_wrap,
otherwise aa=aa+aa_inc, in which the aa is a current value of the address register.
10. The method according to claim 6 , wherein the determining, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to achieve the address buffer management, comprises:
when performing the load or store instruction, determining, according to aa_inc, aa_wrap and aa_test which are obtained through decoding the set instruction, whether to perform the address automatic-increment operation or the address automatic-decrement operation so as to achieve the address buffer management.
11. The method according to claim 10 , wherein
in the case of aa_inc>0 where the aa_inc is the automatic-increment value of an address increment register,
the first intermediate value aa_wrap and the second intermediate value aa_test are obtained from the following operations: aa_wrap=aa_inc−(aa_end-aa_start+1); aa_test=aa_inc−aa_end−1, or
in the case of aa_inc<0 where the aa_inc is the automatic-decrement value of the address increment register,
the first intermediate value aa_wrap and the second intermediate value aa_test are obtained from the following operations: aa_wrap=aa_inc+(aa_end−aa_start+1); aa_test=aa_inc−aa_start.
12. The method according to claim 11 , wherein determining, according to aa_inc, aa_wrap and aa_test, whether to perform the address automatic-increment operation or the address automatic-decrement operation so as to achieve the address buffer management, comprises:
after obtaining the aa_wrap and the aa_test, determining whether a sign bit of the aa_inc is equal to a sign bit of the aa+aa_test so as to achieve the address buffer management,
wherein in the case they are equal, aa=aa+aa_wrap,
otherwise aa=aa+aa_inc, in which the aa is a current value of the address register.