Semiconductor device with air gap spacer and capping barrier layer and method for fabricating the same
A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.
1. A method for fabricating a semiconductor device, the method comprising:
forming an insulation layer over a substrate;
forming an open portion in the insulation layer;
forming a sacrificial spacer over sidewalls of the open portion;
forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion;
forming an ohmic contact layer over the first conductive pattern;
foaming an air gap by removing the sacrificial spacer;
capping the air gap by forming a barrier layer over an entire top surface of the ohmic contact layer and the air gap; and
forming a second conductive pattern over the barrier layer to fill an upper section of the open portion,
wherein capping the air gap further comprises:
forming a first barrier layer over the ohmic contact layer to cap the air gap, wherein the first barrier layer is to cover a top surface and sidewalls of the ohmic contact layer, and to cover the sidewalls of the open portion; and
forming a second barrier layer over the first barrier layer.
2. The method of claim 1 , wherein a portion of the barrier layer that is formed over a top surface and sidewalls of the ohmic contact layer has a first thickness, and a portion of the barrier layer that is formed over the sidewalls of the open portion over the air gap has a second thickness that is less than the first thickness.
3. The method of claim 1 , wherein the first barrier layer is formed by a physical vapor deposition in an ionized metal plasma (PVD-IMP) method.
4. The method of claim 1 , wherein the second barrier layer is formed by a chemical vapor deposition (CVD) method.
5. The method of claim 1 , wherein the first conductive pattern, the ohmic contact layer, and the second conductive pattern form a plug.
6. The method of claim 1 , wherein the first conductive pattern comprises silicon, and the second conductive pattern comprises a metal.
7. The method of claim 1 , further comprising:
performing an annealing process to induce a phase change in the ohmic contact layer after the forming the air gap.
8. The method of claim 7 , wherein the ohmic contact layer includes cobalt silicide having a CoSi x phase (wherein x=about 0.1 to about 1.5), and wherein the causing a phase change in the ohmic contact layer further comprises:
changing, by the annealing process, the cobalt silicide having the CoSi x phase (wherein x=about 0.1 to about 1.5) into cobalt silicide having a CoSi 2 phase.