Piezo-resistive MEMS resonator
A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
1. A method of manufacturing a piezo-resistive MEMS resonator, comprising:
forming an anchor, a resonator body mounted on the anchor and a piezo-resistive read-out means on a silicon on insulator substrate; and
providing an actuator for applying an electrostatic force to the resonator;
wherein the piezo-resistive read-out means includes a nanowire coupled to the resonator, the nanowire being formed by etching and isolating a silicon portion from the silicon-on-insulator layer, and
wherein the resonator body has an area of at least 100 μm 2 and the nanowire has a cross section of at most 10 −14 m 2 .
2. A method as in claim 1 , wherein the etching of the silicon portion comprises:
etching a silicon line of first width; and
oxidizing a portion of the silicon line and etching away the oxidized silicon to form a line of second, smaller width relative to the first width.
3. A method as in claim 2 , wherein the etching of the silicon portion further comprises removing a top portion of the line of second width to define a nanowire portion as a remaining bottom portion.
4. A method as in claim 3 , wherein the removing of the top portion comprises implanting a species which amorphises a portion of the line of second width to a desired depth, and removing the amorphised part of the silicon line of second width.
5. A method as in claim 2 , wherein etching the silicon portion further comprises providing an isolated top portion of the line of second width to define a nanowire portion.
6. A method as in claim 5 , wherein the providing an isolated top portion comprises forming a silicon germanium layer between a lower silicon portion and an upper silicon portion in the region of the nanowire portion, and removing the silicon germanium layer to isolate the upper silicon portion.
7. A method as in claim 1 , wherein the isolated portion has a depth of less than 100 nm and a line width of less than 100 nm.
8. A method as in claim 7 , wherein the isolated portion has a depth of approximately 50 nm.
9. A method as in claim 1 , wherein the etching of the silicon portion further comprises selectively removing silicon with a dry etch, and using a silicon germanium layer to isolate a top portion of the nanowire and the silicon-on-insulator layer beneath.
10. A method as in claim 1 , wherein the etching of the silicon portion further comprises partially oxidizing a portion of the silicon-on-insulator layer, the oxidized portion enveloping a non-oxidized line approximately 50 nm in width, and etching away the oxide portion.
11. A method as in claim 1 , wherein the nanowire has a cross section of at least 5000 nm 2 .
12. A method as in claim 1 , wherein the resonator body has an area of at least 400 μm 2 .
13. A method as in claim 1 , wherein the resonator body is suspended by a hinge defined by the anchor, the anchor further defining the nanowire.