Caching of adaptively sized cache tiles in a unified L2 cache with surface compression
One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.
1. A non-transitory computer-readable storage medium including instructions that, when executed by a processor, cause the processor to adaptively size cache tiles in a graphics system, by performing the steps of:
setting a cache tile size associated with a first cache tile to a first size based on a first render target configuration that includes a first plurality of render targets, wherein the first cache tile is a screen-space tile and is comprised of a plurality of raster tiles, and the size of each raster tile is based on the cache tile size;
detecting a change from the first render target configuration to a second render target configuration that includes a second plurality of render targets, and
setting the cache tile size to a second size by:
determining an amount of cache memory occupied by the cache tile,
calculating a first number of bytes occupied per pixel across the second plurality of render targets,
applying a surface compression factor to the first number of bytes to compute a second number of bytes occupied per compressed pixel, and
calculating the second size based on the second number of bytes.
2. The non-transitory computer-readable medium of claim 1 , further comprising determining that the second plurality of render targets does not comprise a subset of the first plurality of render targets.
3. The non-transitory computer-readable medium of claim 1 , wherein at least one of the first size and the second size corresponds to a cache tile that does not have square dimensions.
4. The non-transitory computer-readable medium of claim 1 , wherein the first size and the second size enable the first cache tile to be stored in a local cache memory residing within a graphics processor.
5. The non-transitory computer-readable medium of claim 4 , wherein at least one of the first size and the second size is set to ensure that the first cache tile occupies no more than a first portion of the local cache memory.
6. The non-transitory computer-readable medium of claim 1 , wherein a first raster tile included in the plurality of raster tiles is processed by a first graphics processing cluster and a second raster tile included in the plurality of raster tiles is processed by a second graphics processing cluster.
7. A method for adaptively sizing cache tiles in a graphics system, the method comprising:
setting a cache tile size associated with a first cache tile to a first size, wherein the first cache tile is a screen-space tile and is comprised of a plurality of raster tiles, and the size of each raster tile is based on the cache tile size, and wherein the raster tiles are processed by a plurality of graphics processing clusters residing within a graphics processor, each graphics processing cluster including a plurality of streaming multiprocessors;
detecting a change from a first render target configuration comprising a first plurality of render targets to a second render target configuration comprising a second plurality of render targets; and
setting the cache tile size to a second size by:
determining an amount of cache memory occupied by the cache tile,
calculating a first number of bytes occupied per pixel across the second plurality of render targets,
applying a surface compression factor to the first number of bytes to compute a second number of bytes occupied per compressed pixel, and
calculating the second size based on the second number of bytes.
8. The method of claim 7 , further comprising determining that the second plurality of render targets does not comprise a subset of the first plurality of render targets.
9. The method of claim 8 , wherein the second cache tile size is based on an amount of memory space allocated to each of the render targets in the second plurality of render targets.
10. The method of claim 9 , wherein calculating the first number of bytes comprises multiplying a number of bytes occupied per pixel across the second plurality of render targets by an anti-aliasing factor.
11. The method of claim 7 , wherein at least one of the first size and the second size corresponds to a cache tile that does not have square dimensions.
12. The method of claim 7 , wherein first cache tile resides in a cache memory within a graphics processor.
13. The method of claim 12 , wherein at least one of the first size and the second size is set to ensure that the first cache tile occupies no more than a first portion of the cache memory.
14. The method of claim 13 , wherein the first portion of the cache memory comprises cache tile data and a second portion of the cache memory comprises texture data and vertex attribute data.
15. The method of claim 13 , wherein a cache controller associated with the cache memory is configured to:
determine that a first data item residing in the first cache tile and a second data item residing in a second portion of the cache memory are directed to the same location in a first render target; and
write the first data item and the second data item to the first render target in a single transaction.
16. The method of claim 13 , wherein a cache controller associated with the cache memory is configured to:
determine that a first data item residing in a first render target and a second data item residing in the first render target are scheduled to be loaded into the first cache tile, wherein the first data item and the second data item are stored in neighboring locations in the first render target; and
read the first data item and the second data item from the first render target in a single transaction.
17. The method of claim 13 , wherein a cache controller associated with the cache memory is configured to:
determine that a first graphics primitive is dependent on a first data item residing in a first render target;
determine that a second graphics primitive is dependent on the first data item; and
read the first data item from the first render target in a single transaction.
18. A graphics system, comprising:
a processing unit; and
a first memory coupled to the processing unit and storing a device driver that is configured to adaptively size cache tiles in the graphics system by:
setting a cache tile size associated with a first cache tile to a first size, wherein the first cache tile is a screen-space tile and is comprised of a plurality of raster tiles, and the size of each raster tile is based on the cache tile size, and wherein the raster tiles are processed by a plurality of graphics processing clusters residing within a graphics processor, each graphics processing cluster including a plurality of streaming multiprocessors;
detecting a change from a first render target configuration comprising a first plurality of render targets to a second render target configuration comprising a second plurality of render targets; and
setting the cache tile size to a second size by:
determining an amount of cache memory occupied by the cache tile,
calculating a first number of bytes occupied per pixel across the second plurality of render targets,
applying a surface compression factor to the first number of bytes to compute a second number of bytes occupied per compressed pixel, and
calculating the second size based on the second number of bytes.
19. The graphics system of claim 18 , further comprising:
a cache memory comprising:
a first portion that includes a cache tile, and
a second portion; and
a cache controller associated with the cache memory configured to:
determine that a first data item residing in the first cache tile and a second data item residing in a second portion of the cache memory are directed to the same location in a first render target; and
write the first data item and the second data item to the first render target in a single transaction.
20. The graphics system of claim 19 , wherein the cache controller is further configured to:
determine that a first data item residing in a first render target and a second data item residing in the first render target are scheduled to be loaded into the first cache tile, wherein the first data item and the second data item are stored in neighboring locations in the first render target; and
read the first data item and the second data item from the first render target in a single transaction.
21. The graphics system of claim 19 , wherein the cache controller is further configured to:
determine that a first graphics primitive is dependent on a first data item residing in a first render target;
determine that a second graphics primitive is dependent on the first data item; and
read the first data item from the first render target in a single transaction.