Managing shared cache by multi-core processor
Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.
1. A processing system, comprising:
a plurality of processing cores comprising an active processing core and an inactive processing core, each processing core communicatively coupled to a respective last level cache (LLC) slice, each LLC slice comprising a first plurality of control cache sets and a second plurality of sample cache sets, each of the control cache sets comprising a first pre-defined number of associative ways and each of the sample cache sets comprises a second pre-defined number of associative ways, wherein the second pre-defined number exceeds the first pre-defined number; and
a cache control logic coupled to the plurality of processing cores, the cache control logic to:
determine a first energy to be consumed to power on an LLC slice of the inactive processing core,
determine a number of misses in the sample cache sets of the active processing core over a sampling period,
determine a number of misses in the control cache sets of the active processing core over the sampling period,
determine a second energy to be consumed to access a random access memory (RAM) if the LLC slice is power gated, as a function of a difference between the number of misses in the sample cache sets and the number of misses in the control cache sets, and
responsive to determining that the second energy exceeds the first energy, make the LLC slice available to the active processing core.
2. The processing system of claim 1 , wherein a processing core of the plurality of processing cores is provided by a cluster comprising two or more processing cores.
3. The processing system of claim 1 , wherein each processing core further comprises a private first level cache.
4. The processing system of claim 3 , wherein each processing core further comprises a private mid-level cache.
5. The processing system of claim 1 , wherein the cache control logic is further to, responsive to determining that the first energy exceeds the second energy, power gate the LLC slice.
6. A method, comprising:
determining, by a processing system comprising a plurality of processing cores including an active processing core and an inactive processing core, a first energy to be consumed to power on a last level cache (LLC) slice of the inactive processing core, wherein the LLC slice comprises a first plurality of control cache sets and a second plurality of sample cache sets, each of the control cache sets comprising a first pre-defined number of associative ways and each of the sample cache sets comprises a second pre-defined number of associative ways, wherein the second pre-defined number exceeds the first pre-defined number;
determine a number of misses in the sample cache sets of the active processing core over a sampling period,
determine a number of misses in the control cache sets of the active processing core over the sampling period,
determining a second energy to be consumed to access a random access memory (RAM) if the LLC slice is power gated, as a function of a difference between the number of misses in the sample cache sets and the number of misses in the control cache sets; and
responsive to determining that the second energy exceeds the first energy, making the LLC slice available to the active processing core.
7. The method of claim 6 , further comprising power gating the LLC slice responsive to determining that the first energy exceeds the second energy.
8. The method of claim 6 , wherein making the LLC slice available to the active processing core comprises preventing the LLC slice from off/on oscillations.
9. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing system comprising a plurality of processing cores including an active processing core and an inactive processing core, cause the computing system to perform operations, comprising:
determining a first energy to be consumed to power on an a last level cache (LLC) slice of the inactive processing core, wherein the LLC slice comprises a first plurality of control cache sets and a second plurality of sample cache sets, each of the control cache sets comprising a first pre-defined number of associative ways and each of the sample cache sets comprises a second pre-defined number of associative ways, wherein the second pre-defined number exceeds the first pre-defined number;
determine a number of misses in the sample cache sets of the active processing core over a sampling period,
determine a number of misses in the control cache sets of the active processing core over the sampling period,
determining a second energy to be consumed to access a random access memory (RAM) if the LLC slice is power gated, as a function of a difference between the number of misses in the sample cache sets and the number of misses in the control cache sets; and
responsive to determining that the second energy exceeds the first energy, making the LLC slice available to the active processing core.
10. The computer-readable non-transitory storage medium of claim 9 , wherein the executable instructions further comprise:
power gating the LLC slice responsive to determining that the first energy exceeds the second energy.
11. The computer-readable non-transitory storage medium of claim 9 , wherein a processing core is provided by a cluster comprising two or more processing cores.
12. The computer-readable non-transitory storage medium of claim 9 , wherein making the LLC slice available to the active processing core comprises preventing the LLC slice from off/on oscillations.
13. The processing system of claim 1 , wherein making the LLC slice available to the active processing core comprises preventing the LLC slice from off/on oscillations.
14. The method of claim 6 , wherein a processing core of the plurality of processing cores is provided by a cluster comprising two or more processing cores.
15. The processing system of claim 1 , wherein the cache control logic is further to:
apply an exponential weighted moving average (EWMA) filter to an average number of missed observed over several sampling periods.
16. The processing system of claim 1 , wherein determining the first energy comprises multiplying an idle power consumption of an LLC slice by a duration of the sampling period.
17. The method of claim 6 , further comprising:
applying an exponential weighted moving average (EWMA) filter to an average number of missed observed over several sampling periods.
18. The method of claim 6 , wherein determining the first energy comprises multiplying an idle power consumption of an LLC slice by a duration of the sampling period.
19. The computer-readable non-transitory storage medium of claim 9 , wherein the executable instructions further comprise: applying an exponential weighted moving average (EWMA) filter to an average number of missed observed over several sampling periods.
20. The computer-readable non-transitory storage medium of claim 9 , wherein determining the first energy comprises multiplying an idle power consumption of an LLC slice by a duration of the sampling period.