Direct memory access (DMA) address translation with a consecutive count field
DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries.
1. A computer system comprising:
at least one processor;
a memory coupled to the at least one processor, the memory having a plurality of real pages that have a corresponding plurality of real page numbers;
a direct memory access (DMA) address translation table in the memory that includes a plurality of entries, each entry comprising:
a pointer to one of the plurality of real page numbers; and
a consecutive count field that defines a number of subsequent translation table entries that point to real page numbers sequential and subsequent to the one real page number; and
a DMA address translation mechanism that adds an entry to the DMA address translation table and writes a value of zero to the consecutive count field for the entry when a subsequent entry immediately following the entry does not point to a next sequential real page number, and writes a value greater than zero to the consecutive count field for the entry when the subsequent entry points to the next sequential real page number.
2. The computer system of claim 1 wherein the DMA address translation mechanism updates the consecutive count field of any other entries affected by adding the entry to the DMA address translation table.
3. The computer system of claim 2 wherein one of the other entries is affected by adding the entry to the DMA translation table when the entry points to a real page number that is adjacent the real page number of the affected entry.
4. The computer system of claim 1 wherein the DMA address translation mechanism reads a selected entry in the DMA translation table, and when the selected entry has a non-zero value in the consecutive count field, and when a DMA transfer spans a plurality of subsequent successive translation table entries that includes the selected entry, the DMA address translation mechanism returns the real page number for the selected entry and returns at least one subsequent real page number based on the consecutive field count without accessing any corresponding entry in the DMA address translation table.
5. The computer system of claim 1 wherein each entry further comprises a maximum consecutive count field that defines a number of preceding entries that point to real page numbers sequential to and preceding the one real page number.
6. The computer system of claim 1 wherein the DMA address translation table comprises at least one indirect translation table and a final translation table that includes the pointer to the one real page number.
7. The computer system of claim 1 further comprising a DMA address translation cache that stores a plurality of the DMA address translation entries.
8. A computer system comprising:
at least one processor;
a memory coupled to the at least one processor, the memory having a plurality of real pages that have a corresponding plurality of real page numbers;
a direct memory access (DMA) address translation table in the memory that includes a plurality of entries, each entry comprising: a pointer to one of the plurality of real page numbers;
a consecutive count field that defines a number of subsequent entries that point to real page numbers sequential and subsequent to the one real page number; and
a maximum consecutive count field that defines a number of preceding entries that point to real page numbers sequential to and preceding the one real page number;
a DMA address translation mechanism that adds an entry to the DMA address translation table and writes a value of zero to the consecutive count field for the entry when a subsequent entry immediately following the entry does not point to a next sequential real page number, and writes a value greater than zero to the consecutive count field for the entry when the subsequent entry points to the next sequential real page number, the DMA address translation mechanism updating the consecutive count field of any other entries affected by adding the entry to the DMA address translation table, wherein one of the other entries is affected by adding the entry to the DMA translation table when the entry points to a real page number that is adjacent the real page number of the affected entry, wherein the DMA address translation mechanism reads a selected entry in the DMA translation table, and when the selected entry has a non-zero value in the consecutive count field, and when a DMA transfer spans a plurality of subsequent successive entries that includes the selected entry, the DMA address translation mechanism returns the real page number for the selected entry and returns at least one subsequent real page number based on the consecutive field count without accessing any corresponding entry in the DMA address translation table.
9. The computer system of claim 8 wherein the DMA address translation table comprises at least one indirect translation table and a final translation table that includes the pointer to the one real page number.