Semiconductor memory device
A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line. A line is selectively connected to a gate electrode of the selection transistor, a driver, or a node that supplies an unselected voltage, or is set to be in a floating state.
1. A semiconductor memory device comprising:
a string of memory cell transistors that are connected to each other in series;
a first selection transistor that is connected between a first end of the string of the memory cell transistors and a source line, a gate of the first selection transistor being connected to a first line;
a second selection transistor that is connected between a second end of the string of the memory cell transistors and a bit line, a gate of the second selection transistor being connected to a second line;
a driver configured to generate selected and unselected voltages for the first and second transistors;
transfer transistors between the driver and the first and second selection transistors, the transfer transistors being controllable to set at least one of the first and second lines to be in a floating state;
a first latch configured to hold information about whether or not a block containing the string of memory cell transistors is a bad block; and
a second latch configured to hold information about whether or not one of the first and second lines is to be set in a floating state.
2. The semiconductor memory device according to claim 1 , wherein
the second latch is configured to hold information about whether or not the first line is to be set in a floating state.
3. The semiconductor memory device according to claim 2 , wherein the transfer transistors include a first transfer transistor between a selected voltage source and the first line, and a second transfer transistor between an unselected voltage source and the first line, the first line being set in the floating state when the first and second transfer transistors are both turned off.
4. The semiconductor memory device according to claim 1 , wherein
the second latch is configured to hold information about whether or not the second line is to be set in a floating state.
5. The semiconductor memory device according to claim 4 , wherein the transfer transistors include a first transfer transistor between a selected voltage source and the second line, and a second transfer transistor between an unselected voltage source and the second line, the second line being set in the floating state when the first and second transfer transistors are both turned off.
6. A semiconductor memory device comprising:
a string of memory cell transistors that are connected to each other in series;
a first selection transistor that is connected between a first end of the string of the memory cell transistors and a source line, a gate of the first selection transistor being connected to a first line;
a second selection transistor that is connected between a second end of the string of the memory cell transistors and a bit line, a gate of the second selection transistor being connected to a second line;
a driver configured to generate selected and unselected voltages for the first and second transistors;
transfer transistors between the driver and the first and second selection transistors, the transfer transistors being controllable to set at least one of the first and second lines to be in a floating state;
a first latch configured to hold information about whether or not the first line is to be set in a floating state; and
a second latch configured to hold information about whether or not the second line is to be set in a floating state.
7. The semiconductor memory device according to claim 1 , further comprising:
a block decoder that generates block select and block non-select signals that are used to control the transfer transistors to be switched on or off.
8. A semiconductor memory device comprising:
a block including,
a string of memory cell transistors that are connected to each other in series; and
a selection transistor that is connected between one end of the string of the memory cell transistors and one of a source line and a bit line;
a line that is connected to a gate electrode of the selection transistor;
a first transistor;
a first latch configured to hold a first data about whether or not a block containing the string of memory cell transistors is a bad block;
a second latch configured to hold a second data; and
a logic circuit that is electrically connected to the second latch,
wherein one end of the first transistor is connected to the first line, and an output end of the logic circuit is connected to a gate of the first transistor.
9. The semiconductor memory device according to claim 8 , further comprising:
a second transistor connected between a driver that supplies a selected voltage and the line wherein the line is connected to a node that supplies an unselected voltage through the first transistor.
10. The semiconductor memory device according to claim 9 , further comprising:
a latch that, when set, causes the first and second transfer transistors to be turned off.
11. The semiconductor memory device according to claim 9 , further comprising:
a first latch that, when set, causes the first and second transistors to be turned off; and
a second latch that, when set, causes the first transistor to be turned on and the second transistor to be turned off.
12. The semiconductor memory device according to claim 9 , further comprising:
a first latch that, when set, causes the first and second transistors to be turned off; and
a second latch that, when set and the first latch is not set, causes the first transistor to be turned on and the second transistor to be turned off, and when set and the first latch is set, the first and second transistors are turned off.
13. The semiconductor memory device according to claim 9 , wherein the first and second transistors are turned off during reading and writing processes, but not during an erasing process.
14. The semiconductor memory device according to claim 8 , wherein the selection transistor is connected between the one end of the string of the memory cell transistors and the source line.
15. The semiconductor memory device according to claim 8 , wherein the selection transistor is connected between the one end of the string of the memory cell transistors and the bit line.
16. A semiconductor memory device comprising:
a string of memory cell transistors that are connected to each other in series;
a selection transistor that is connected between one end of the string of the memory cell transistors and one of a source line and a bit line;
a line that is connected to a gate electrode of the selection transistor, is connected to a driver through a first transfer transistor, and is connected to a first node that supplies an unselected voltage through a second transfer transistor;
a block decoder configured to generate block select and block non-select signals that are used to control the first and second transfer transistors to be switched on and off;
a first latch that, when set, holds information indicating non-selection of the line even when an address for selecting the line is input thereto; and
a second latch that, when set, causes the first and second transfer transistors to be turned off.
17. The semiconductor memory device according to claim 16 , wherein the first and second transfer transistors are turned off during reading and writing processes, but not during an erasing process.
18. The semiconductor memory device according to claim 16 , wherein the selection transistor is connected between the one end of the string of the memory cell transistors and the source line.
19. The semiconductor memory device according to claim 16 , wherein the selection transistor is connected between the one end of the string of the memory cell transistors and the bit line.