Apparatus and method of programming and verification for a nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a memory cell array comprising memory strings, each of the memory strings comprising memory cells connected in series;

bit lines connected to the memory strings, respectively;

word lines connected to the memory cells, respectively, and connected to the memory strings in common; and

a control circuit configured to repeat a program operation of applying a program pulse voltage to a selected word line and programming data in selected memory cells connected to the selected word line, and a verify operation of checking threshold voltages of the selected memory cells,

wherein the control circuit performs a first verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage, wherein the first threshold voltage is less than the second threshold voltage,

wherein the control circuit performs a charging operation and then performs a sensing operation,

wherein the control circuit charges a first bit line for the first verify operation to a first charge voltage and charges a second bit line for the second verify operation to a second charge voltage in the charging operation, the second charge voltage being different from the first charge voltage,

wherein the control circuit senses discharge states of the charged first and second bit lines in the sensing operation,

wherein the first charge voltage and the second charge voltage are not 0V, and

wherein the control circuit simultaneously performs the first verify operation and the second verify operation.

2. The device of claim 1 , wherein the second charge voltage is lower than the first charge voltage.

3. The device of claim 1 , wherein a sensing time of the second verify operation is longer than a sensing time of the first verify operation.

4. The device of claim 1 , wherein the control circuit uses a same verify voltage applied to the selected word line in the first verify operation and the second verify operation.

5. The device of claim 1 , wherein:

the control circuit performs the first verify operation again for a memory cell, for which the first verify operation has passed and the second verify operation has failed, when a predetermined number of program loops have been performed, and

the control circuit finishes the program operation of the memory cell when the first verify operation has passed.

6. The device of claim 1 , wherein the control circuit finishes the program operation for a memory cell, for which the first verify operation has passed and the second verify operation has failed, when a predetermined number of program loops has been performed.

7. The device of claim 1 , wherein:

the control circuit performs the program operation by applying a first voltage to a bit line connected to a memory cell, for which the first verify operation has failed, and

the control circuit performs the program operation by applying a second voltage to a bit line connected to a memory cell, for which the first verify operation has passed and the second verify operation has failed, wherein the first voltage is less than the second voltage.

8. The device of claim 7 , wherein the control circuit performs the program operation by applying the first voltage to the bit line connected to the memory cell, for which the first verify operation has passed and the second verify operation has failed, when a predetermined number of program loops has been performed.

9. The device of claim 1 , wherein the control circuit starts the verify operation after program operations are successively performed.

10. The device of claim 9 , wherein:

the control circuit performs the first verify operation and the second verify operation with a same bit-line charge voltage in the verify operation started directly after the program operations are successively performed, and

a sensing time of the second verify operation is longer than a sensing time of the first verify operation in the started verify operation.

11. The device of claim 1 , wherein the control circuit does not charge bit lines connected to memory cells not to be verified among the bit lines.

12. The device of claim 1 , wherein each of the memory cells includes a charge storage layer.

13. A nonvolatile semiconductor memory device comprising:

a memory cell array comprising memory strings, each of the memory strings comprising memory cells connected in series;

bit lines connected to the memory strings, respectively;

word lines connected to the memory cells, respectively, and connected to the memory strings in common; and

a control circuit configured to perform a previous read operation of reading data of adjacent memory cells connected to an adjacent word line adjacent to a selected word line, and a read operation of reading data of selected memory cells connected to the selected word line in accordance with a previous read result obtained by the previous read operation,

wherein the read operation includes a charging operation and a sensing operation after the charging operation,

wherein the control circuit charges first and second bit lines respectively to first and second charge voltages in accordance with the previous read result, in the charging operation, the second charge voltage being different from the first charge voltage,

wherein the control circuit senses discharge states of the charged first and second bit lines in the sensing operation,

wherein the first charge voltage and the second charge voltage are not 0V, and

wherein the control circuit simultaneously performs the read operation of the selected memory cells.

14. The device of claim 13 , wherein a charge voltage for the bit lines is set to a lower value for a bit line connected to a selected memory cell having a larger shift amount of a threshold voltage due to inter-cell interference with an adjacent memory cell.

15. The device of claim 13 , wherein the control circuit applies a fixed read pass voltage to the adjacent word line in the read operation, the read pass voltage being configured to turn on the adjacent memory cells regardless of storage data.

16. The device of claim 15 , wherein the control circuit applies the same read pass voltage to word lines other than the selected word line and the adjacent word line among the word lines, in the read operation.

17. The device of claim 13 , wherein the control circuit applies a read voltage to the selected word line in the read operation, the read voltage being configured to determine threshold voltages of the selected memory cells.

18. The device of claim 13 , wherein each of the memory cells includes a charge storage layer.

19. A nonvolatile semiconductor memory device comprising:

a memory cell array comprising memory strings, each of the memory strings comprising memory cells connected in series;

bit lines connected to the memory strings, respectively;

word lines connected to the memory cells, respectively, and connected to the memory strings in common; and

a control circuit configured to repeat a program operation of applying a program pulse voltage to a selected word line and programming data in selected memory cells connected to the selected word line, and a verify operation of checking threshold voltages of the selected memory cells,

wherein the control circuit performs a first verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage, wherein the first threshold voltage is less than the second threshold voltage,

wherein the control circuit performs a charging operation and then performs a sensing operation,

wherein the control circuit charges a first bit line for the first verify operation to a first charge voltage and charges a second bit line for the second verify operation to a second charge voltage in the charging operation, the second charge voltage being different from the first charge voltage,

wherein the control circuit senses discharge states of the charged first and second bit lines in the sensing operation,

wherein the first charge voltage and the second charge voltage are not 0V, and

wherein the second charge voltage is lower than the first charge voltage.