Device and method for eliminating complex operations in processing systems based on caching
The technology described in this application relates generally to computing processing systems and more specifically relates to systems that process data with resource intensive operations. Method and apparatus to lower the power consumption of the resource intensive operations are disclosed. Code analysis methods and run-time apparatus are presented that may eliminate the redundant operations (either complex calculations, memory fetches, or both). The techniques presented in this application are driven by special instructions inserted in the software code of the executing computer programs during the code generation process. Code analysis methods to insert the special instructions into the appropriate points in the source code of the target executing computer programs are presented. Run-time hardware mechanisms to support the potential elimination of redundant operations are also presented. Corresponding methods that might increase the number of eliminated operations by allowing limited errors to occur are also disclosed.
1. In an instruction set computer, a device, which is part of a processing path of the instruction set computer, to perform memorization to predict results of code segments without executing the code segments, the device comprising:
means for receiving dedicated value cache machine instructions at a start and end of each of a plurality of code segments;
means for receiving arguments associated with each of the plurality of code segments;
means for storing a most recently received N arguments and M results associated with each of the plurality of code segments, wherein N and M are positive integers;
means for storing one or more expected branch offsets for each of the plurality of code segments;
means for searching for a set of input parameters within the means for storing;
means for notifying of a cache hit when the set of input parameters matches the stored arguments associated with a particular one of the plurality of code segments stored in the means for storing;
means for returning the results associated with the particular one of the plurality of code segments;
means for altering an instruction flow to branch to one of the one or more expected branch offsets associated with the particular one of the plurality of code segments; and
means for updating the means for storing when the set of input parameters does not match any of the stored arguments.
2. The device of claim 1 , wherein the input parameters are in a floating point format.
3. The device of claim 1 , wherein the input parameters are in a fixed point format.
4. The device of claim 1 , wherein matching of the input parameters to the stored arguments can be performed using a reduced precision than that of the input parameters.
5. The device of claim 1 , wherein the input parameters are commutative.
6. The device of claim 1 , wherein the input parameters can be transformed to a sign-independent format.
7. The device of claim 1 , wherein the one or more expected branch offsets comprises a plurality of branch offsets, and wherein one of the plurality of branch offsets is selected based on a partial matching of the input parameters to the stored arguments.
8. The device of claim 1 incorporated into a graphics processing unit vertex, fragment, or unified shader processor.
9. The device of claim 1 incorporated into a general purpose processor.
10. The device of claim 1 , wherein performance and a cache hit ratio are monitored by circuitry.
11. An apparatus comprising the device of claim 1 , wherein the apparatus:
monitors a cache hit rate of the device; and
enables or disables the device based on the cache hit rate.
12. A value caching method in an instruction set computer, the method comprising:
searching computer code and identifying independent code segments having specific input parameters and results;
inserting dedicated value cache machine instructions at a start and end of each of the identified independent code segments, wherein the value cache machine instruction at the end of each of the identified independent code segments updates a value cache;
receiving a value cache machine instruction associated with a particular code segment, the received value cache machine instruction including input parameters;
searching the value cache based on the input parameters, wherein the value cache stores one or more arguments, one or more outputs, and one or more branch offsets associated with each of a plurality of code segments;
determining a cache hit when the input parameters match the one or more arguments associated with a particular code segment stored in the value cache;
branching to one of the one or more branch offsets associated with the particular code segment when there is a cache hit; and
executing the particular code segment when there is not a cache hit.
13. The method of claim 12 , wherein the dedicated value cache machine instructions are inserted and removed based on performance criteria.
14. The method of claim 12 , wherein the dedicated value cache machine instructions are inserted and removed based on energy consumption criteria.
15. The method of claim 12 , wherein the dedicated value cache machine instructions are inserted and removed based on user-defined criteria.
16. The method of claim 12 , wherein the dedicated value cache machine instructions are inserted and removed based on an effect on performance of previous execution of each independent code segment.
17. The method of claim 12 , wherein a number of cache hits is dynamically adjusted by reducing a precision required in the determining a match between the input parameters and the stored one or more arguments.
18. The method of claim 12 , wherein the computer code includes an indication of commutativity of input parameters.
19. The method of claim 12 , wherein the input parameters are transformed to a sign-independent format.