Granted Patent B1

US 8,878,711 · App. 14/015,294 · Granted Nov 4, 2014

Abstract

Claims (34)

1. A system, comprising:

an input to receive a communication signal;

an integrator connected with the input, the integrator to determine an integrated signal from the communication signal;

a comparator, an output of the integrator connected with an input of the comparator, the comparator to quantize the integrated signal to produce a quantized signal;

a digital-to-analog convertor connected between an output of the comparator and the output of the integrator and connected between the output of the comparator and an input of the integrator, the digital-to-analog convertor to convert the quantized signal to a delayed analog signal; and

a compensation element connected with the digital-to-analog convertor, the compensation element to adjust a weight of the delayed analog signal, the comparator to receive the adjusted, delayed analog signal.

2. The system of claim 1 , where the compensation element comprises a passive summer.

3. The system of claim 2 , where the passive summer comprises a plurality of resistors or switched capacitors.

4. The system of claim 1 , where the compensation element adjusts for a reduction in power of the integrator.

5. The system of claim 1 , further comprising an out-of-band flattening element connected between the input and the comparator.

6. The system of claim 5 , where the out-of-band flattening element comprises a resistor or a switched capacitor.

7. The system of claim 1 , where the digital-to-analog convertor comprises a finite impulse response digital-to-analog convertor.

8. The system of claim 1 , where the compensation element comprises a programmable resistor or a programmable switched capacitor.

9. An analog-to-digital converter, comprising:

an input to receive a communication signal;

an integrator connected with the input, the integrator to determine an integrated signal from a communication signal;

a comparator connected with the integrator, the comparator to quantize the integrated signal to produce a quantized signal; and

a flattening element connected between an output of the integrator and the input, the flattening element to flatten an out-of-band signal transfer function of the integrator.

10. The analog-to-digital converter of claim 9 , further including an adjustable delay element to provide a delayed quantized signal to the comparator.

11. The analog-to-digital converter of claim 10 , where the adjustable delay element comprises a finite impulse response digital-to-analog convertor.

12. The analog-to-digital converter of claim 9 , further including a compensation element connected with the comparator to adjust for a reduction in power of the integrator or compensate for a delay.

13. The analog-to-digital converter of claim 12 , where the compensation element comprises a programmable resistor or a programmable switched capacitor.

14. The analog-to-digital converter of claim 12 , where the compensation element comprises a passive summer.

15. The analog-to-digital converter of claim 9 , where the flattening element comprises a resistor or a switched capacitor.

16. A method for converting an analog signal to a digital signal, comprising:

integrating an input signal with a plurality of integrators;

comparing, with a comparator, the integrated signals to a determined value to provide a quantized signal;

delaying the quantized signal;

adjusting the delayed signal with a compensation element; and

inputting the adjusted signal to the comparator.

17. The method of claim 16 , further comprising, summing outputs of the plurality of integrators before the comparing.

18. The method of claim 16 , further comprising converting the quantized signal to an analog signal before the adjusting.

19. The method of claim 18 , further comprising compensating for a reduction in power of at least one of the integrators.

20. The method of claim 16 , further comprising reducing out-of-band signal transfer functions.

Assignments (6)