Nonvolatile semiconductor memory device with a three-dimensional structure in which sub-blocks are independently erasable

1. A nonvolatile semiconductor memory device comprising:

a memory cell array which includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks;

a control unit configured to change a verification voltage to be applied to a selected word line included in a selected sub-block when data is written, depending on whether or not data is written in a non-selected sub-block; and

flag cells which are respectively provided in the plurality of sub-blocks and store flag data indicating whether or not data is written in the sub-blocks,

wherein when the flag data which is stored in the flag cell in the non-selected sub-block indicates writing, the control unit sets the verification voltage to be higher than when the flag data does not indicate writing in the non-selected sub-block.

2. The device according to claim 1 ,

wherein during writing, the control unit applies a first verification voltage to a first word line on a source side of the selected sub-block and applies a second verification voltage which is higher than the first verification voltage to a second word line farther toward a drain side than the first word line.

3. The device according to claim 2 ,

wherein when data is written in the non-selected sub-block, the control unit applies a third verification voltage which is higher than the second verification voltage to a third word line on a source side of the selected sub-block and applies a fourth verification voltage which is higher than the second verification voltage to a fourth word line farther toward a drain side than the third word line.

4. The device according to claim 1 , wherein each of the word lines commonly connects a memory cell from each of the memory strings.

5. The device according to claim 1 , wherein the memory cell array is a three-dimensional memory cell array.

6. A method of writing data in a nonvolatile semiconductor memory device comprising a memory cell array which includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks and including flag data indicating whether or not data is written therein, said method comprising:

selecting a sub-block for writing;

determining whether or not data is written in a non-selected sub-block by reading the flag data corresponding to the non-selected sub-block; and

changing a verification voltage to be applied to a selected word line included in the selected sub-block based on said determining,

wherein when the flag data corresponding to the non-selected sub-block indicates writing, setting the verification voltage to be higher than when the flag data does not indicate writing in the non-selected sub-block.

7. The method according to claim 6 ,

wherein during writing, applying a first verification voltage to a first word line on a source side of the selected sub-block and applying a second verification voltage which is higher than the first verification voltage to a second word line farther toward a drain side than the first word line.

8. The method according to claim 7 ,

wherein when data is written in the non-selected sub-block, applying a third verification voltage which is higher than the second verification voltage to a third word line on a source side of the selected sub-block and applying a fourth verification voltage which is higher than the second verification voltage to a fourth word line farther toward a drain side than the third word line.

9. The method according to claim 6 , wherein each of the word lines commonly connects a memory cell from each of the memory strings.

10. The method according to claim 6 , wherein the memory cell array is a three-dimensional memory cell array.

11. The method according to claim 6 , further comprising:

writing data to the selected sub-block; and

verifying the data written to the selected sub-block by supplying the verification voltage to the selected word line.