Semiconductor integrated circuit including a voltage boosting or lowering circuit
View Patent ↗A semiconductor integrated circuit includes a reference voltage generation circuit configured to generate a reference voltage, and a voltage changing circuit configured to generate a second voltage from a first voltage based on a difference between the second voltage and the reference voltage and apply the second voltage to a load capacitance. The reference voltage generation circuit includes a variable current source and a capacitor which are connected in series and is configured to change the reference voltage linearly.
1. A semiconductor integrated circuit comprising:
a reference voltage generation circuit configured to generate a reference voltage;
a first differential amplifier circuit configured to compare a monitored voltage generated from a voltage that is applied to a load capacitance, with the reference voltage and output a first difference signal;
a second differential amplifier circuit configured to compare the monitored voltage with the reference voltage and output a second difference signal;
a voltage boosting circuit configured to generate a boosted voltage that is applied to the load capacitance from a first power supply voltage based on the first difference signal; and
a voltage lowering circuit configured to generate a lowered voltage that is applied to the load capacitance from a second power supply voltage based on the second difference signal, wherein
the reference voltage generation circuit includes a variable current source and a capacitor which are connected in series, and is configured to change the reference voltage linearly.
2. The semiconductor integrated circuit according to claim 1 , wherein the reference voltage generation circuit is controlled to change the reference voltage linearly during a period from a point of time at which changing of the voltage applied to the load capacitance is started to a point of time at which the changed voltage reaches a predetermined value.
3. The semiconductor integrated circuit according to claim 1 , wherein
the reference voltage generation circuit is controlled to change the reference voltage at a first change rate during a first time period and at a second change rate that is different from the first change rate during a second time period.
4. The semiconductor integrated circuit according to claim 1 , further comprising:
a memory cell array including a plurality of planes of memory cells; and
a selection circuit configured to select at least one of the planes,
wherein the load capacitance changes depending on a number of planes selected by the selection circuit.
5. The semiconductor integrated circuit according to claim 4 , wherein
the reference voltage generation circuit is controlled to change the reference voltage at a change rate that is determined according to the number of planes selected by the selection circuit.
6. A semiconductor integrated circuit comprising:
a reference voltage generation circuit including a variable current source and a capacitor which are connected in series;
a first differential amplifier circuit having a first input electrically connected to an output of the reference voltage generation circuit to receive a reference voltage generated by the reference voltage generation circuit, a second input to which a monitored voltage generated from an output voltage is supplied, wherein the first differential amplifier circuit generates a first difference signal based on a difference between the reference voltage and the monitored voltage;
a second differential amplifier circuit having a first input electrically connected to the output of the reference voltage generation circuit to receive the reference voltage generated by the reference voltage generation circuit, a second input to which the monitored voltage is supplied, wherein the second differential amplifier circuit generates a second difference signal based on a difference between the reference voltage and the monitored voltage;
a voltage boosting circuit that boosts the output voltage based on a first power supply voltage and on the first difference signal; and
a voltage lowering circuit that lowers the output voltage based a second power supply voltage and on the second difference signal.
7. The semiconductor integrated circuit according to claim 6 , wherein the reference voltage generation circuit is controlled to change the reference voltage linearly during a period from a point of time at which changing of the output voltage is started to a point of time at which the changed output voltage reaches a predetermined value.
8. The semiconductor integrated circuit according to claim 6 , wherein
the reference voltage generation circuit is controlled to change the reference voltage at a first change rate during a first time period and at a second change rate that is different from the first change rate during a second time period.
9. The semiconductor integrated circuit according to claim 6 , further comprising:
a memory cell array including a plurality of planes of memory cells; and
a selection circuit configured to select at least one of the planes,
wherein the output voltage is changed depending on a number of planes selected by the selection circuit.
10. The semiconductor integrated circuit according to claim 9 , wherein
the reference voltage generation circuit is controlled to change the reference voltage at a change rate that is determined according to the number of planes selected by the selection circuit.