Semiconductor storage device

1. A semiconductor storage device, comprising:

a plurality of memory cells that each comprise a variable resistance element;

a plurality of first wires and a plurality of second wires, wherein each memory cell is disposed between and electrically coupled to one of the plurality of first wires and one of the plurality of second wires; and

a control circuit that is configured to:

apply a set voltage (V s ) having a first polarity for a set voltage application time (T s ) to a first memory cell during a set operation in which the variable resistance element is changed to a set state having a first threshold voltage in the first polarity;

apply a reset voltage having a second polarity being opposite to the first polarity to the first memory cell during a reset operation in which the variable resistance element is changed to a reset state having a second threshold voltage larger than the first threshold voltage in the first polarity; and

apply a cancel voltage (V cancel ) having the first polarity for a cancel voltage application time (T cancel ) to a second memory cell in the reset operation, wherein the second memory cell is applied a certain voltage when the reset voltage is applied to the first memory cell, the absolute value of the certain voltage is less than the absolute value of the reset voltage,

wherein the relationship between the set voltage (V s ), the set voltage application time (T s ), the cancel voltage (V cancel ) and the cancel voltage application time (T cancel ) satisfies,

-

Vs

ln

⁡

(

Ts

A

)

>

-

2

⁢

Vcancel

ln

⁡

(

Tcancel

A

)

,

wherein A is a constant.

2. The semiconductor storage device of claim 1 , wherein the variable resistance element in the first memory cell and the second memory cell each comprise silicon oxide.

3. The semiconductor storage device of claim 2 , wherein A equals 1000.

4. The semiconductor storage device of claim 1 , wherein the variable resistance element in the first memory cell and the second memory cell each comprise silicon.

5. The semiconductor storage device of claim 4 , wherein A equals 6100.

6. The semiconductor storage device of claim 1 , wherein the reset voltage is applied for a first period of time, and the control circuit is further configured to apply a weak reset voltage of the second polarity to the second memory cell for a second period of time, and the absolute value of the weak reset voltage value is smaller than the absolute value of the reset voltage or the second period of time is smaller than the first period of time.

7. The semiconductor storage device of claim 1 , wherein the absolute value of the cancel voltage is smaller than the absolute value of the set voltage.

8. The semiconductor storage device according to claim 1 , wherein

the applying the reset voltage to the first memory cell during the reset operation further comprises:

applying a first reset voltage to a selected first wire;

applying a second reset voltage to a selected second wire; and

applying a third reset voltage to unselected first wires and unselected second wires, and

the applying the cancel voltage (V cancel ) further comprises:

applying a first cancel voltage to the selected first wire;

applying a second cancel voltage to the selected second wire; and

applying a third cancel voltage to the unselected first wires and the unselected second wires, and

wherein the third reset voltage and the third cancel voltage have the same voltage values.

9. The semiconductor storage device of claim 1 , wherein the absolute value of the cancel voltage (V cancel ) is about one half of the absolute value of the reset voltage.

10. The semiconductor storage device of claim 1 , wherein the control circuit is configured to apply another voltage having the second polarity to the first memory cell during the reset operation.

11. A method of using a semiconductor storage device having a plurality of memory cells that each comprise a variable resistance element, a plurality of first wires and a plurality of second wires, wherein each memory cell is disposed between and electrically coupled to one of the plurality of first wires and one of the plurality of second wires, and a control circuit, said method comprising:

applying a set voltage (V s ) having a first polarity for a set voltage application time (T s ) to a first memory cell during a set operation in which the variable resistance element is changed to a set state that conduct at a first voltage in the first polarity;

applying a reset voltage having a second polarity which is opposite to the first polarity to the first memory cell during a reset operation in which the variable resistance element is changed to a reset state that conducts at a second voltage which is larger than the first voltage in the first polarity; and

applying a cancel voltage (V cancel ) being the first polarity for a cancel voltage application time (T cancel ) to a second memory cell in the reset operation,

wherein the second memory cell is applied a certain voltage when the reset voltage is applied to the first memory cell, the absolute value of the certain voltage being less than the absolute value of the reset voltage, wherein the relationship between the set voltage (V s ), the set voltage application time (T s ), the cancel voltage (V cancel ) and the cancel voltage application time (T cancel ) satisfies,

-

Vs

ln

⁡

(

Ts

A

)

>

-

2

⁢

Vcancel

ln

⁡

(

Tcancel

A

)

,

and wherein A is a constant.

12. The method of claim 11 , wherein the variable resistance element in the first memory cell and the second memory cell each comprise silicon oxide.

13. The method of claim 12 , wherein A equals 1000.

14. The method of claim 11 , wherein the variable resistance element in the first memory cell and the second memory cell each comprise silicon.

15. The method of claim 14 , wherein A equals 6100.

16. The method of claim 11 , wherein the reset voltage is applied for a first period of time, and the method further comprises:

applying a weak reset voltage of the second polarity to the second memory cell for a second period of time, and the absolute value of the weak reset voltage value is smaller than the absolute value of the reset voltage or the second period of time is smaller than the first period of time.

17. The method of claim 11 , wherein the absolute value of the cancel voltage is smaller than the absolute value of the set voltage.

18. The method of claim 11 , wherein the absolute value of the cancel voltage (V cancel ) is about one half of the absolute value of the reset voltage.

19. The method of claim 11 , wherein the control circuit that is configured to apply another voltage having the second polarity to the first memory cell during the reset operation.

20. The method of claim 11 , wherein

the applying the reset voltage to the first memory cell during the reset operation further comprises:

applying a first reset voltage to the selected first wire;

applying a second reset voltage to the selected second wire; and

applying a third reset voltage to unselected first wires and unselected second wires, and

the applying a cancel voltage (V cancel ) further comprises:

applying a first cancel voltage to the selected first wire;

applying a second cancel voltage to the selected second wire; and

applying a third cancel voltage to the unselected first wires and the unselected second wires, wherein applying the first cancel voltage, applying the second cancel voltage and applying the third cancel voltage are done at the same time, and

wherein the third reset voltage and the third cancel voltage have the same voltage values.