IP Library Granted Patent US 9,104,596
Granted Patent B2
US 9,104,596 · App. 14/017,259 · Granted Aug 11, 2015

Memory system

Inventor: Hiroshi Yao (Kanagawa, JP)
Assignee: Kabushiki Kaisha Toshiba
G06F11/1048
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Quick Facts
Patent No.
US 9,104,596
App. No.
14/017,259
Granted
Aug 11, 2015
Kind
B2
Abstract

According to one embodiment, a memory device includes a memory unit including a first subunit and a second subunit, a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data, and a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the second write data and the second redundant data to be written in the second subunit. The control unit is configured to control the code encoding unit to start calculation of the second redundant data after all of the writing steps for writing the first write data and the first redundant data have been carried out.

Claims (60)

1. A memory device comprising:

a memory unit including a first subunit and a second subunit;

a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data; and

a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the second write data and the second redundant data to be written in the second subunit,

wherein the first and second write data and the first and second redundant data are written through a plurality of writing steps, in each of which a part of data is written, at least one of the writing steps for writing the second write data and the second redundant data being carried out before all of the writing steps for writing the first write data and the first redundant data have been carried out, and

wherein the control unit is configured to control the code encoding unit to start calculation of the second redundant data after all of the writing steps for writing the first write data and the first redundant data have been carried out.

2. The memory device according to claim 1 , further comprising:

a buffer unit configured to store first calculation data used to calculate the first redundant data and second calculation data used to calculate the second redundant data,

wherein the control unit is configured to control the buffer unit to delete the first calculation data before storing the second calculation data.

3. The memory device according to claim 1 , further comprising:

a buffer unit configured to store first calculation data used to calculate the first redundant data and second calculation data used to calculate the second redundant data,

wherein the control unit is configured to control the buffer unit to delete the first calculation data after the first write data and the first redundant data have been written in the first subunit.

4. The memory device according to claim 1 , wherein

the control unit is configured to control the code encoding unit to start calculation of the second redundant data before all of the writing steps for writing the second redundant data are carried out.

5. The memory device according to claim 1 , wherein

each of the first and second subunits includes a plurality of lines, a plurality of memory cells being connected to each of the lines, and the writing steps being carried out with respect to each of the lines, and

the second redundant data starts to be calculated during a first writing step with respect to one or more of the lines.

6. The memory device according to claim 5 , wherein

the second redundant data is not calculated during a first writing step with respect to at least one of the lines.

7. The memory device according to claim 6 , wherein

a first writing step with respect to one of the lines of the second subunit in which a part of the second write data is written is carried out before a second writing step with respect to one of the lines of the first subunit in which a part of the first redundant data is written.

8. A method for writing data in a memory device including a first memory unit and a second memory unit, the method comprising:

calculating first redundant data based on first write data;

writing the first write data and the first redundant data in the first memory unit through a plurality of writing steps, in each of which a part of the first write data or a part of the first redundant data is written;

starting calculation of second redundant data based on second write data after all of the writing steps for writing the first write data and the first redundant data have been carried out; and

writing the second write data and the second redundant data in the second memory unit through a plurality of writing steps, in each of which a part of the second write data or a part of the second redundant data is written,

wherein at least one of the writing steps for writing the second write data and the second redundant data is carried out before all of the writing steps for writing the first write data and the first redundant data have been carried out.

9. The method according to claim 8 , further comprising:

storing first calculation data used to calculate the first redundant data and second calculation data used to calculate the second redundant data; and

deleting the first calculation data before the second calculation data is stored.

10. The method according to claim 8 , further comprising:

storing first calculation data used to calculate the first redundant data and second calculation data used to calculate the second redundant data; and

deleting the first calculation data after the first write data and the first redundant data have been written in the first memory unit.

11. The method according to claim 10 , wherein

each of the first and second subunits includes a plurality of lines, a plurality of memory cells being connected to each of the lines, and the writing steps being carried out with respect to each of the lines, and

the second redundant data starts to be calculated during a first writing step with respect to one or more of the lines.

12. The method according to claim 11 , wherein

the second redundant data is not calculated during a first writing step with respect to at least one of the lines.

13. The method according to claim 12 , wherein

a first writing step with respect to one of the lines of the second subunit in which a part of the second write data is written is carried out before a second writing step with respect to one of the lines of the first subunit in which a part of the first redundant data is written.

14. The method according to claim 8 , wherein

the second redundant data starts to be calculated before all of the writing steps for writing second redundant data are carried out.

15. A memory device comprising:

a memory unit including a plurality of memory blocks, each of which includes a first line group and a second line group, data being written in memory cells connected to each line of the first and second line groups,

a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data; and

a control unit configured to cause the first write data and the first redundant data to be written in the memory cells along each line of the first line groups with respect to each of the memory blocks in parallel and the second write data and the second redundant data to be written in the memory cells along each line of the second line groups with respect to each of the memory blocks in parallel,

wherein the first and second write data and the first and second redundant data are written through a plurality of writing steps with respect to each line of the first and second line groups, in each of which a part of data is written, at least one of the writing steps for writing the second write data and the second redundant data being carried out before all of the writing steps for writing the first write data and the first redundant data have been carried out, and

wherein the control unit is configured to control the code encoding unit to start calculation of the second redundant data after all of the writing steps for writing the first write data and the first redundant data have been carried out.

16. The memory device according to claim 15 , further comprising:

a buffer unit configured to store first calculation data used to calculate the first redundant data and second calculation data used to calculate the second redundant data,

wherein the control unit is configured to control the buffer unit to delete the first calculation data before storing the second calculation data.

17. The memory device according to claim 15 , further comprising:

a buffer unit configured to store first calculation data used to calculate the first redundant data and second calculation data used to calculate the second redundant data,

wherein the control unit is configured to control the buffer unit to delete the first calculation data after the first write data and the first redundant data have been written in the first subunit.

18. The memory device according to claim 15 , wherein

the control unit is configured to control the code encoding unit to start calculation of the second redundant data before all of the writing steps for writing the second redundant data are carried out.

19. The memory device according to claim 15 , wherein

the second redundant data starts to be calculated during a first writing step with respect to one or more of the lines of the second line group.

20. The memory device according to claim 19 , wherein

the second redundant data is not calculated during a first writing step with respect to at least one of the lines of the second line group.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043221/0723 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2013
From: YAO, HIROSHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 031853/0890 →
Priority Claims (1)
JP 2013-000939 · Jan 8, 2013 · national
Continuity (1)
Related Publication 20140195874A1 · Jul 10, 2014