IP Library Granted Patent US 9,007,118
Granted Patent B2
US 9,007,118 · App. 14/018,981 · Granted Apr 14, 2015

Circuit for combining signals

Inventor: Neale Dutton (Edinburgh, GB)
Assignee: STMicroelctronics (Research & Development) Limited
G06G7/12H03K5/1534
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Quick Facts
Patent No.
US 9,007,118
App. No.
14/018,981
Granted
Apr 14, 2015
Kind
B2
Abstract

Signals generated by an array of photodiodes are applied to the inputs of corresponding edge detection circuits. Each edge detection circuit generates an output that changes state in response to a detected edge of the photodiode generated signal. The edge detection circuits may be formed by toggle flip-flop circuits. The outputs of the edge detection circuits are logically combined using exclusive OR logic to generate an output. The exclusive OR logic may be formed by a cascaded tree of exclusive OR circuits.

Claims (25)

1. A circuit comprising:

a plurality of edge detectors each having an input configured to receive an input signal and an output configured to output a first output signal, each edge detector operable to change a state of the first output signal in response to an edge of the input signal; and

a plurality of exclusive OR circuits configured to receive a plurality of first output signals from the plurality of edge detectors and operable to combine the plurality of first output signals to generate a second output signal.

2. The circuit of claim 1 , wherein one or more of the edge detectors comprises a toggle element.

3. The circuit of claim 2 , wherein the toggle element comprises a T-type flip flop.

4. The circuit of claim 2 , wherein the toggle element comprises a plurality of coupled inverters with interposing transmission gates.

5. The circuit of claim 1 , wherein the plurality of exclusive OR circuits comprise a cascaded tree of exclusive OR circuits.

6. The circuit of claim 1 , wherein the input signal is a signal output from a radiation sensitive element.

7. The circuit of claim 6 , wherein the radiation sensitive element comprises a single photon avalanche diode.

8. A proximity sensor, comprising:

an array of radiation sensitive elements; and

a circuit comprising:

a plurality of edge detectors each having an input configured to receive an input signal and an output configured to output a first output signal, each edge detector operable to change a state of the first output signal in response to an edge of the input signal; and

a plurality of exclusive OR circuits configured to receive a plurality of first output signals from the plurality of edge detectors and operable to combine the plurality of first output signals to generate a second output signal.

9. The sensor of claim 8 , wherein each radiation sensitive element comprises a single photon avalanche diode.

10. The sensor of claim 8 , wherein each edge detector comprises a toggle flip-flop.

11. The sensor of claim 8 , wherein the plurality of exclusive OR circuits comprises a cascaded tree of exclusive OR circuits.

12. A signal combination method, comprising:

receiving a plurality of input signals;

detecting an edge of each of said plurality of input signals;

changing a state of a corresponding first output signal in response to the detected edge of said input signal; and

exclusive ORing a plurality of said corresponding first output signals to provide a combined second output signal using a plurality of exclusive OR circuits.

13. The method of claim 12 , further comprising outputting signals from an array of radiation sensitive elements, each radiation sensitive element output signal comprising one of said plurality of input signals.

14. The method of claim 13 , wherein the radiation sensitive elements comprise single photon avalanche diodes.

15. The method of claim 12 , wherein exclusive ORing comprises combining the plurality of said corresponding first output signals in a cascaded exclusive OR tree.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2022
From: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 060341/0033 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2013
From: DUTTON, NEALE
To: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
Reel/Frame 031145/0134 →
Priority Claims (1)
GB 1216116.2 · Sep 10, 2012 · national
Continuity (1)
Related Publication 20140070867A1 · Mar 13, 2014