Semiconductor device, information processing system including same, and controller for controlling semiconductor device
View Patent ↗A system includes a control chip and a plurality of command terminals receiving a plurality of command signals, respectively; a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and a layer address buffer configured to output a layer address each time the command decoder outputs a row command as the internal command and outputs a column command as the internal command; and a plurality of core chips stacked with one another, each of the core chips being configured to receive the, row command and the layer address output together with the row command, to receive the column command and the layer address output together with the column command, and to free from receiving the command signals.
1. A system comprising:
a control chip including:
a plurality of command terminals receiving a plurality of command signals, respectively;
a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and
a layer address buffer configured to output a layer address each time the command decoder outputs a row command as the internal command and outputs a column command as the internal command; and
a plurality of core chips stacked with one another, each of the core chips being configured to receive the, row command and the layer address output together with the row command, to receive the column command and the layer address output together with the column command, and to free from receiving the command signals.
2. The system as claimed, in claim 1 , wherein the control chip is stacked with the core chips.
3. The system as claimed in claim 1 , wherein the control chip includes a clock terminal to receive an external clock signal and an internal clock generating circuit to generate an Internal clock signal based on the external clock signal, each of the core chips being configured to receive the internal clock signal and to be free from receiving the external clock signal.
4. The system as claimed in claim 1 , wherein each of the core chips includes a plurality of memory cells to store data and the controller is free from a memory cell.
5. The system as claimed in claim 1 , wherein the core chips include layer address generating circuits, respectively, and the layer address generating circuits are connected in series such that an Output node of a preceding one of the layer address generating circuits is connected to an input node of a succeeding one of the layer address generating circuits.
6. The system as claimed in claim 5 , wherein the row command is performed on a selected one of the core chips when layer information stored in the layer address generating circuit of the selected one of the core chips is coincident with the layer address output together with the row command.
7. The system as claimed in claim 5 , wherein the column command is performed on the selected one of the core chips when the layer information stored in the layer address generating circuit of the selected one of the core chips is coincident with the layer address output together with the column command.