Hardware and operating system support for persistent memory on a memory bus

1. A processor comprising:

a control component that enforces ordering and atomicity of memory writes;

a memory component to enforce timing restraints in addition to the ordering and the atomicity enforced by the control component;

a non-volatile memory that is addressable by the control component; and

a dynamic random access memory (DRAM), which shares an address space with the non-volatile memory;

wherein the memory component comprises:

a scheduler component that provides timing to the control component; and

a memory controller transaction component that includes data to be flushed according to the timing provided by the scheduler component.

2. The processor of claim 1 , wherein the control component enforces ordering of memory writes by assigning epoch identifiers (epoch IDs).

3. The processor of claim 1 , wherein a persistence bit is used by the memory component to reference data that is to be written in the non-volatile memory.

4. A circuit comprising:

a first component to enforce ordering and atomicity of writes to a memory component, the memory component addressable by the first component and including a non-volatile memory which shares an address space with a dynamic random access memory (DRAM); and

a second component coupled to the first component to enforce timing restraints on the writes in addition to the ordering and the atomicity enforced by the first component;

wherein the memory component comprises:

scheduler component that provides timing to the first component; and

a memory controller transaction component that includes data to be flushed according to the timing provided by the scheduler component.

5. The circuit of claim 4 , wherein the first component enforces ordering of the writes by assigning epoch identifiers (epoch IDs).

6. The circuit of claim 4 , wherein the second component enforces ordering of the writes based in part on a persistence bit and a dirty block counter.

7. The circuit of claim 4 , wherein the first component is a central processing unit (CPU) and the second component is a memory controller.

8. The circuit of claim 4 , wherein the non-volatile memory is phase change memory (PCM).

9. The circuit of claim 4 , wherein the non-volatile memory is byte-addressable.

10. The circuit of claim 4 , wherein the DRAM is used for stack or heap to improve wear lifetime of the non-volatile memory.

11. A processor comprising:

a persistent memory addressable by a control component to enforce ordering of writes; and a dynamic random access memory (DRAM), which shares an address space with the persistent memory;

a scheduler component that provides timing to the persistent memory; and

a memory controller transaction component that includes data to be flushed according to the timing provided by the scheduler component.

12. The processor of claim 11 , further comprising a memory component to enforce timing restraints in addition to the ordering enforced by the control component.

13. The processor of claim 11 , wherein the persistent memory is byte-addressable.

14. The processor of claim 11 , wherein the persistent memory is capable of using small and random writes to reduce traffic in a memory bus.

15. The processor of claim 11 , wherein the persistent memory is phase change memory (PCM).

16. The processor of claim 11 , wherein the control component enforces ordering of the writes by assigning an epoch identifier (epoch ID) to the writes.

17. The processor of claim 11 , wherein the control component enforces ordering of the writes based in part on a persistence bit and a dirty block counter.

18. The processor of claim 11 , wherein the control component is a central processing unit (CPU).

19. The processor of claim 11 , further comprising a memory bus coupled to the control component, the persistent memory and the DRAM, wherein the persistent memory is addressable by the control component via the memory bus.